Word line bias during stripe erase in a memory device
AssigneeSanDisk Technologies LLC
InventorsParth Amin, Anubhav Khandelwal
Life of this patent
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Abstract
The memory device includes a memory block with an array of memory cells that are arranged in edge word lines and non-edge word lines. Some of the word lines are in a first group to be erased in a first pulse and the others are in a second group to be erased in a second pulse. Circuitry is configured to erase the memory cells. In the first erase pulse, the circuitry applies a first inhibit voltage to the non-edge word lines of the second group and applies a higher second inhibit voltage to the edge word lines of the second group. In the second erase pulse, the circuitry applies the first inhibit voltage to the non-edge word lines of the first group and applies the higher second inhibit voltage to the edge word lines of the second group.
Claims20
A method of performing an erasing operation in a memory device, comprising the steps of:
- preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a plurality of edge word lines and a plurality of non-edge word lines, the plurality of word lines also including a first group of word lines to be erased in a first erase pulse of an erase loop and a second group of word lines to be erased in a second erase pulse of the erase loop;
- in the first erase pulse, applying a first inhibit voltage to the non-edge word lines of the second group of word lines and applying a higher second inhibit voltage to the edge word lines of the second group of word lines;
- and
- in the second erase pulse, applying the first inhibit voltage to the non-edge word lines of the first group of word lines and applying the higher second inhibit voltage to the edge word lines of the second group of word lines.
A memory device, comprising:
- a memory block that includes an array that has a plurality of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a plurality of edge word lines and a plurality of non-edge word lines, the plurality of word lines also including a first group of wordlines to be erased in a first erase pulse of an erase loop and a second group of word lines to be erased in a second erase pulse of the erase loop;
- circuitry configured to erase the plurality of memory cells in the memory block in an erasing operation, during the erasing operation, the circuitry being configured to:
- in the first erase pulse, apply a first inhibit voltage to the non-edge word lines of the second group of word lines and apply a higher second inhibit voltage to the edge word lines of the second group of word lines;
- and in the second erase pulse, apply the first inhibit voltage to the non-edge word lines of the first group of word lines and apply the higher second inhibit voltage to the edge word lines of the second group of word lines.
An apparatus, comprising:
- a memory block that includes an array with a plurality of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a plurality of edge word lines and a plurality of non-edge word lines, the plurality of word lines also including a first group of word lines to be erased in a first erase pulse of an erase loop and a second group of word lines to be erased in a second erase pulse of the erase loop;
- an erasing means for erasing the plurality of memory cells in the memory block in an erasing operation, during the erasing operation, the erasing means being configured to:
- in the first erase pulse, apply a first inhibit voltage to the non-edge word lines of the second group of word lines and apply a higher second inhibit voltage to the edge wordlines of the second group of word lines, the higher second inhibit voltage being equal to the first inhibit voltage plus a bias voltage;
- and in the second erase pulse, apply the first inhibit voltage to the non-edge word lines of the first group of word lines and apply the higher second inhibit voltage to the edge word lines of the second group of word lines.
Dependencies are inferred from the claim text.