Semiconductor memory device and operating method of the same

A programming method of a semiconductor memory device, the semiconductor memory device including a substrate, the semiconductor memory device including a memory cell array which includes a plurality of memory cells, each memory cell configured to store a plurality of bits, a plurality of word lines connected to the plurality of memory cells and extending in a first direction on the substrate, and a plurality of bit lines connected to the plurality of memory cells and extending in a second direction intersecting the first direction, the semiconductor memory device including a voltage generator configured to generate a voltage applied to the memory cell array, the semiconductor memory device including a control logic configured to control the voltage generator, the word lines including a first word line, the plurality of memory cells including a first memory cell group, the first word line connected to the first memory cell group, the programming method comprising:

• applying an erase voltage to the substrate to perform an erase operation on the plurality of memory cells corresponding to the plurality of word lines, the erase voltage is a positive (+) erase voltage;
• subsequently to performing the erase operation, performing a first program operation, the first program operation including applying a first program voltage to the first word line so that the first memory cell group has a first threshold voltage, the first program voltage is a positive (+) first program voltage;
• subsequently to performing the first program operation, performing a first verification operation on the first memory cell group based on a first verification voltage, the first verification voltage smaller than the first threshold voltage;
• and
• performing a second verification operation on the first memory cell group based on a second verification voltage, the second verification voltage greater than the first threshold voltage.

A programming method of a semiconductor memory device which includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells and extending in a first direction on a substrate, a plurality of bit lines connected to the plurality of memory cells and extending in a second direction intersecting the first direction, and a control logic, the programming method comprising:

• applying an erase voltage to the substrate to perform an erase operation on the plurality of memory cells, the erase voltage is a positive (+) erase voltage;
• selecting a first word line among the plurality of word lines, the first word line connected to a first memory cell group and a second memory cell group among the plurality of memory cells;
• applying a first program voltage to the first word line so that the first memory cell group has a first threshold voltage, applying a bit line program voltage to a first bit line connected to the first memory cell group, and applying an inhibit voltage to a second bit line connected to the second memory cell group, the first program voltage is a positive (+) first program voltage;
• applying a first verification voltage to the first word line, the first verification voltage smaller than the first threshold voltage;
• applying a first correction voltage to the first word line, the first correction voltage is a positive (+) first correction voltage, the first correction voltage greater than the first program voltage;
• applying a second verification voltage to the first word line, the second verification voltage greater than the first threshold voltage;
• applying a second correction voltage to the first word line, the second correction voltage is a negative (−) second correction voltage, an absolute value of the second correction voltage equal to or smaller than an absolute value of the first correction voltage;
• applying a second program voltage to the first word line so that the second memory cell group has a second threshold voltage, applying the inhibit voltage to the first bit line, and applying the bit line program voltage to the second bit line, the second program voltage is a positive (+) second program voltage, the second threshold voltage greater than the first threshold voltage;
• applying a third verification voltage to the first word line, the third verification voltage smaller than the second threshold voltage;
• applying a third correction voltage to the first word line, the third correction voltage is a positive (+) third correction voltage, the third correction voltage greater than the second program voltage;
• applying a fourth verification voltage to the first word line, the fourth verification voltage greater than the second threshold voltage;
• and
• applying a fourth correction voltage to the first word line, the fourth correction voltage is a negative (−) fourth correction voltage, an absolute value of the fourth correction voltage equal to or smaller than an absolute value of the third correction voltage.