Ternary content-addressable memory cells and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorGerben Doornbos
Life of this patent
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Abstract
A four transistor ternary content-addressable memory cell includes a first series connection of a first non-hysteretic transistor (e.g., a thin-film transistor) and a first memory transistor (e.g., a thin-film transistor) including a first memory element configured to store a first binary bit; and a second series connection of a second non-hysteretic transistor and a second memory transistor including a second memory element configured to store a second binary bit. The first series connection and the second series connection are connected in parallel between a match line and a word line.
Claims20
A device structure comprising a four transistor ternary content-addressable memory cell, which comprises:
- a first series connection of a first non-hysteretic transistor and a first memory transistor comprising a first memory element configured to store a first binary bit;
- a second series connection of a second non-hysteretic transistor and a second memory transistor comprising a second memory element configured to store a second binary bit, wherein the first series connection and the second series connection are connected in parallel between a match line and a word line;
- a primary bit line connected to a gate electrode of the first memory transistor;
- and
- a complementary bit line connected to a gate electrode of the second memory transistor.
A device structure comprising:
- a first dielectric material layer overlying a substrate;
- a first series connection of a first non-hysteretic transistor and a first memory transistor comprising a first memory element configured to store a first binary bit, the first series connection overlying the first dielectric material layer;
- a second series connection of a second non-hysteretic transistor and a second memory transistor comprising a second memory element configured to store a second binary bit, wherein the first non-hysteretic transistor, the first memory transistor, the second non-hysteretic transistor, and the second memory transistor are embedded in a second dielectric material layer;
- and
- a match line and a word line embedded in a third dielectric material layer, wherein the first series connection and the second series connection are connected in parallel between the match line and the word line.
A method of forming a device structure, the method comprising:
- forming a first memory transistor, a second memory transistor, a first non-hysteretic transistor, and a second non-hysteretic transistor, wherein the first memory transistor comprises a first memory element configured to store a first binary bit, and the second memory transistor comprises a second memory element configured to store a second binary bit;
- forming a first series connection of the first memory transistor and the first non-hysteretic transistor;
- forming a second series connection of the second memory transistor and the second non-hysteretic transistor;
- forming a four transistor ternary content-addressable memory cell by forming a match line and a word line and by connecting the first series connection and the second series connection in parallel between the match line and the word line;
- forming a first contact via structure directly on the first memory transistor and the first non-hysteretic transistor to provide the first series connection;
- and
- forming a second contact via structure directly on the second memory transistor and the second non-hysteretic transistor to provide the second series connection.
Dependencies are inferred from the claim text.