Radiation hardened E-FUSE macro

A method of writing a multi-bit, asynchronous e-fuse macro, the method comprising:

• providing a write address for a plurality of e-fuse bits with a write address bus in operative communication with a plurality of e-fuse bits;
• performing signaling by a self-timing and control circuitry;
• applying power from a supply voltage to the e-fuse macro while grounding the supply voltage;
• asserting a power on reset while de-asserting a ground clamp enable, an input output enable, a write clock, and a write enable;
• setting the write address and asserting the write enable;
• applying the supply voltage to the e-fuse macro;
• pulsing the write clock to program an e-fuse memory element;
• grounding or floating the supply voltage;
• and
• de-asserting the write enable.

A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for reading or writing a multi-bit, asynchronous e-fuse macro, wherein the e-fuse macro is configured to support two operating modes, an application mode configured to allow reading from the e-fuse macro and a programming mode configured to allow writing to the e-fuse macro, the process comprising:

• when in the application mode, the process comprises:
• providing a write address for a plurality of e-fuse bits using a write address bus in operative communication with the plurality of e-fuse bits;
• performing signaling by a self-timing and control circuitry;
• applying power from a supply voltage to the e-fuse macro, wherein the supply voltage is either grounded or floating;
• asserting a power on reset, a precharge, a ground clamp enable, and an output enable while de-asserting a write clock;
• de-asserting the power on reset;
• reading the e-fuse bits upon de-asserting the power on reset via the self-timing and control circuitry, producing e-fuse memory element;
• storing the e-fuse memory element in at least one latch;
• and
• outputting the e-fuse memory element stored in the at least one latch to a fuse output;
• when in the programming mode, the process comprises:
• providing a write address for the plurality of e-fuse bits with a write address bus in operative communication with the plurality of e-fuse bits;
• performing signaling by a self-timing and control circuitry;
• applying power from a supply voltage to the e-fuse macro while grounding the supply voltage;
• asserting a power on reset while de-asserting a ground clamp enable, an input output enable, a write clock, and a write enable;
• setting the write address and asserting the write enable;
• applying the supply voltage to the e-fuse macro;
• pulsing the write clock to program an e-fuse memory element;
• grounding or floating the supply voltage;
• and
• de-asserting the write enable.