Field-programmable gate array (FPGA) configurable cell with P and N pass gates to same bit line

A field-programmable logic device comprising:

• a configurable switching fabric having a plurality of fabric cells, wherein each fabric cell comprises:
• a SRAM cell that comprises:
• a first pull-up transistor and a first pull-down transistor connected in series between a memory upper power supply and a memory lower power supply, the first pull-up transistor and the first pull-down transistor connected at a first latch node;
• a second pull-up transistor and a second pull-down transistor connected in series between the memory upper power supply and the memory lower power supply, the second pull-up transistor and the second pull-down transistor connected at a second latch node;
• wherein gates of the first pull-up transistor and of the first pull-down transistor are driven by the second latch node between the second pull-up transistor and the second pull-down transistor;
• wherein gates of the second pull-up transistor and of the second pull-down transistor are driven by the first latch node between the first pull-up transistor and the first pull-down transistor;
• a first n-channel pass transistor connected between the first latch node and a first write bit line, and having a gate connected to a write word line;
• a second n-channel pass transistor connected between the second latch node and a second write bit line, and having a gate connected to the write word line;
• a first p-channel pass transistor connected between the first latch node and the first write bit line, and having a gate connected to an inverse write word line;
• a second p-channel pass transistor connected between the second latch node and the second write bit line, and having a gate connected to the inverse write word line;
• a switch cell that comprises:
• a p-channel switch transistor having a gate connected to the second latch node from the SRAM cell, and a channel that conducts current controlled by the gate between a switch input node and a switch output node;
• and
• an n-channel switch transistor having a gate connected to the first latch node from the SRAM cell, and a channel that conducts current controlled by the gate between the switch input node and the switch output node;
• wherein reading and writing during a configuration mode are performed by activating the write word line high and the inverse write word line low;
• wherein during writing configuration data is driven onto the first write bit line and an inverse of the configuration data is driven onto the second write bit line;
• a plurality of configurable logic blocks, each configurable logic block comprising:
• a SRAM cell that comprises:
• a third pull-up transistor and a third pull-down transistor connected in series between the memory upper power supply and the memory lower power supply, the third pull-up transistor and the third pull-down transistor connected at a third latch node;
• a fourth pull-up transistor and a fourth pull-down transistor connected in series between the memory upper power supply and the memory lower power supply, the fourth pull-up transistor and the fourth pull-down transistor connected at a fourth latch node;
• wherein gates of the third pull-up transistor and of the third pull-down transistor are driven by the fourth latch node between the fourth pull-up transistor and the fourth pull-down transistor;
• wherein gates of the fourth pull-up transistor and of the fourth pull-down transistor are driven by the third latch node between the third pull-up transistor and the third pull-down transistor;
• a third n-channel pass transistor connected between the third latch node and a third write bit line, and having a gate connected to a second word line;
• a fourth n-channel pass transistor connected between the fourth latch node and a fourth write bit line, and having a gate connected to the second word line;
• a third p-channel pass transistor connected between the third latch node and the third write bit line, and having a gate connected to an inverse second word line;
• a fourth p-channel pass transistor connected between the fourth latch node and the fourth write bit line, and having a gate connected to the inverse second word line;
• a logic cell that comprises:
• a p-channel switch transistor having a gate connected to the fourth latch node from the SRAM cell, and a channel that conducts current controlled by the gate between the memory upper power supply and an upper node;
• a p-channel select transistor having a gate receiving an inverse of a first logic signal and having a channel that connects current controlled by the gate between the upper node and a cell output node;
• an n-channel select transistor having a gate receiving the first logic signal and having a channel that connects current controlled by the gate between the cell output node and a lower node;
• an n-channel switch transistor having a gate connected to the fourth latch node from the SRAM cell, and a channel that conducts current controlled by the gate between the lower node and the memory lower power supply;
• wherein reading and writing during the configuration mode are performed by activating the second word line high and the inverse second word line low;
• wherein during writing configuration data is driven onto the third write bit line and an inverse of the configuration data is driven onto the fourth write bit line;
• a voltage booster that receives a standard upper power supply and generates the memory upper power supply, the voltage booster increasing a standard power supply voltage of the standard upper power supply to a boosted power supply voltage of the memory upper power supply;
• wherein the memory upper power supply voltage is at least 0.05 volt greater than the standard power supply voltage;
• wherein the voltage booster is enabled for mission mode;
• wherein the memory upper power supply is shunted to the standard upper power supply when the voltage booster is not enabled;
• wherein the configuration data is written into the SRAM cell only during configuration mode and never during mission mode;
• and
• a voltage reducer that receives a standard lower power supply and generates the memory lower power supply, the voltage reducer decreasing a standard lower power supply voltage of the standard lower power supply to a reduced power supply voltage of the memory lower power supply;
• wherein the memory lower power supply voltage is at least 0.05 volt less than the standard lower power supply voltage;
• wherein the voltage reducer is enabled for mission mode and disabled for configuration mode;
• wherein the configuration data is written into the SRAM cell only during configuration mode and never during mission mode.