Semiconductor memory device transitioning to standby mode in between two operations

A semiconductor memory device comprising:

• a first memory cell;
• a first word line connected to the first memory cell;
• a first bit line connected to the first memory cell;
• a second memory cell;
• a second word line connected to the second memory cell;
• and
• a second bit line connected to the second memory cell,
• wherein:
• the semiconductor memory device is configured to perform:
• a first operation which is a read operation or a write operation to the first memory cell;
• and
• a second operation which is a read operation or a write operation to the second memory cell,
• the semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set,
• the semiconductor memory device performs a charge share operation to equalize voltages of the first word line and the second word line after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode, and
• the semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.