Computing system performing duty cycle adjuster training and duty cycle adjuster training method thereof

A computing system adjusting a duty cycle of four mutually orthogonal internal clock signals through a duty cycle adjuster (DCA) code, comprising:

• a memory device configured to generate a data signal and/or a data strobe signal having a changed duty cycle in response to a code value of the DCA code;
• and
• a memory controller configured to perform a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and to perform a second training operation after performing the first training operation, the second training operation selecting a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to the reference internal clock signal,
• wherein memory controller is configured to generate a score by measuring an eye window size in units of two unit intervals of the data signal output from the memory device during the first training operation.

A training method of a memory device that adjusts a characteristic of a data signal and/or of a data strobe signal by receiving a duty cycle adjuster (DCA) code, comprising:

• performing a first training of writing a test code to select a first DCA code corresponding to a first internal clock signal and selecting a code by measuring an eye window size of an output data signal;
• and
• after performing the first training, performing a second training of writing a test combination code to select a combination code of a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal and measuring an eye window size of the output data signal,
• wherein in the first training, the eye window size of the data signal is measured in units of two unit intervals.