Storage circuit with gain-cell and self-refresh unit connected between gain-cell and latch circuit
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsJui-Jen Wu, Ping-Chun Wu, Win-San Khwa, Meng-Fan Chang
Life of this patent
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Abstract
In this disclosure, a storage circuit is provided. The storage circuit includes a gain-cell, a self-refresh unit, and a latch circuit. The gain-cell is configured to store first data in a gate of a storage transistor. The self-refresh unit is configured to read the first data from the gain-cell and write the first data back to the gain-cell. The latch circuit is configured to read the first data from the self-refresh unit and latch the first data.
Claims20
A storage circuit, comprising:
- a gain-cell, configured to store first data in a gate of a storage transistor;
- a self-refresh unit, configured to read the first data from the gain-cell and write the first data back to the gain-cell and comprises:
- a refresh inverter, electrically coupled between a first reference potential and a second reference potential;
- and
- a pre-charge transistor, configured to pre-charge a read bit line to the first reference potential during a latch operation of a latch circuit and discharge a write bit line to the second reference potential during the latch operation of the latch circuit;
- and
- the latch circuit, configured to read the first data from the self-refresh unit and latch the first data.
A self-refresh unit, electrically coupled between a gain-cell and a latch circuit, wherein the self-refresh unit comprises:
- a refresh inverter, electrically coupled between a first reference potential and a second reference potential;
- and
- a pre-charge transistor, configured to pre-charge a read bit line to the first reference potential during a latch operation of the latch circuit and discharge a write bit line to the second reference potential during the latch operation of the latch circuit,
- wherein the self-refresh unit is configured to read first data from the gain-cell and write the first data back to the gain-cell, and
- the self-refresh unit is configured to provide the first data to the latch circuit for latching the first data.
A memory array, comprising:
- a plurality of gain-cells, arranged in a matrix of rows and columns, wherein each of the plurality of gain-cells is configured to store first data in a gate of a storage transistor;
- a plurality of self-refresh units, wherein each of the plurality of self-refresh units is electrically coupled to a column of the gain-cells and is configured to read the first data from the column of the gain-cells and write the first data back to the column of the gain and each of the plurality of self-refresh units comprises:
- a refresh inverter, electrically coupled between a first reference potential and a second reference potential;
- and
- a pre-charge transistor, configured to pre-charge a read bit line to the first reference potential during a latch operation of one of a plurality of latch circuits and discharge a write bit line to the second reference potential during the latch operation of the one of the plurality of latch circuits;
- and
- the plurality of latch circuits, wherein each of the plurality of latch circuits is electrically coupled to the column of the gain-cells and is configured to read the first data from each of the plurality of self-refresh units and latch the first data.
Dependencies are inferred from the claim text.