Apparatuses and methods for controlling steal rates
OwnerTimothy B. Cowles, Jiyun Li +6inventors
InventorsTimothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Abstract
An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
Claims19
A memory device, comprising:
- a memory array comprising a plurality of word lines, wherein at least one word line of the plurality of word lines is an aggressor row;
- a refresh control circuit comprising:
- a first victim address generator configured to generate a first type of row address corresponding to +/−1 physically adjacent neighboring rows of the aggressor row in the memory array;
- a second victim address generator configured to generate a second type of row address corresponding to +/−2 physically adjacent neighboring rows of the aggressor row in the memory array,
- wherein the refresh control circuit is configured to provide the first type of row address at a first rate and the second type of row address at a second rate, wherein the first rate is greater than the second rate;
- and
- at least one component configured to set the first rate and second rate.
A method, comprising:
- receiving a refresh command at a memory device:
- generating, with a refresh control circuit, a first victim row address corresponding to a first victim row in a memory array of the memory device based, at least in part, on an aggressor row in the memory array;
- refreshing the first victim row at a first rate;
- generating, with the refresh control circuit a second victim row address corresponding to a second victim row in the memory array based, at least in part, on the aggressor row in the memory array;
- refreshing the second victim row at a second rate;
- generating, with the refresh control circuit, row addresses corresponding to rows in the memory array;
- and
- auto-refreshing the rows in the memory array at a third rate.
An apparatus comprising:
- a memory array comprising a plurality of word lines, wherein at least one word line of the plurality of word lines is an aggressor row;
- a refresh control circuit comprising at least one victim address generator configured to generate a plurality of types of row addresses corresponding to the plurality of word lines, wherein the refresh control circuit is configured to provide the plurality of types of row addresses for refresh operations performed at corresponding ones of a plurality of rates on the plurality of word lines of the memory array;
- and
- a row decoder configured to perform the refresh operations based on row addresses provided from the refresh control circuit, wherein word lines corresponding to a first type of row addresses of the plurality of types of row addresses are refreshed at a first rate of the plurality of rates and word lines corresponding to a second type of row addresses of the plurality of types of row addresses are refreshed at a second rate of the plurality of rates,
- wherein word lines associated with the first type of row addresses have a first physical relationship with the aggressor row and word lines associated with the second type of row addresses have a second physical relationship with the aggressor row;
- and
- at least one component configured to set the plurality of rates.
Dependencies are inferred from the claim text.