Memory cell arrangement and method of reading a capacitive memory cell

A memory cell arrangement, comprising:

• a bitline, a wordline, and a plateline;
• a capacitive memory cell connected to and addressable via the bitline, the wordline, and the plateline;
• a control circuit configured to carry out a read-out operation to read out a memory state of the capacitive memory cell, wherein, for carrying out the read-out operation, the control circuit is configured:
• charge the bitline to a first characteristic voltage by applying a plateline voltage having a first plateline read voltage value at the plateline and by applying a wordline voltage at the corresponding wordline;
• decrease the plateline voltage from the first plateline read voltage value to a second plateline read voltage value to thereby discharge the corresponding bitline from the first characteristic voltage to a second characteristic voltage;
• and
• determine the memory state of the capacitive memory cell based on sensing the second characteristic voltage.

A method of reading a capacitive memory cell which is connected to a bitline, a plateline, and a wordline, the method comprising:

• charging the bitline to a first characteristic voltage by applying a plateline voltage having a first plateline read voltage value at the plateline and by applying a wordline voltage at the wordline;
• decreasing the plateline voltage from the first plateline read voltage value to a second plateline read voltage value to thereby discharge the bitline from the first characteristic voltage to a second characteristic voltage;
• and
• determining a memory state of the capacitive memory cell based on sensing the second characteristic voltage.