Non-linear polar material based multi-capacitor bit-cell with shared gain element and access transistor

An apparatus comprising:

• a first plurality of capacitors, wherein a first individual capacitor of the first plurality of capacitors is coupled to a first node and a first individual plate-line;
• a second plurality of capacitors, wherein a second individual capacitor of the second plurality of capacitors is coupled to a second node and a second individual plate-line;
• a first transistor having a first gate terminal coupled to a first control, wherein the first transistor is coupled to the first node;
• a second transistor having a second gate terminal coupled to a second control, wherein the second transistor is coupled to the second node;
• a third node, wherein the first transistor and the second transistor are coupled to the third node;
• a third transistor having a third gate terminal coupled to the third node, wherein the third transistor has a third drain terminal coupled to a reference, wherein the third transistor has a third source terminal coupled to a sense-line;
• a fourth transistor coupled to the first node and a bit-line;
• and
• a fifth transistor coupled to the second node and the bit-line.

A system comprising:

• a memory to store instructions;
• a processor circuitry to execute the instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
• a first plurality of capacitors, wherein a first individual capacitor of the first plurality of capacitors is coupled to a first node and a first individual plate-line;
• a second plurality of capacitors, wherein a second individual capacitor of the second plurality of capacitors is coupled to a second node and a second individual plate-line;
• a first transistor having a first gate terminal coupled to a first control, wherein the first transistor is coupled to the first node;
• a second transistor having a second gate terminal coupled to a second control, wherein the second transistor is coupled to the second node;
• a third node, wherein the first transistor and the second transistor are coupled to the third node;
• a third transistor having a third gate terminal coupled to the third node, a source terminal coupled to a sense-line, and a drain terminal coupled to a reference;
• and
• a fourth transistor coupled to the third node and a bit-line.