Apparatus and methods for decoder modules for non-volatile memory

A non-volatile memory comprising:

• a memory array comprising a plurality of non-volatile memory cells;
• a first decoder module coupled to the memory array, the first decoder module comprising:
• a first word line decoder comprising a first selector circuit;
• a first bit line decoder comprising a second selector circuit;
• a first bus coupled to a first bias node, the first selector circuit and the second selector circuit;
• a second bus coupled to a second bias node, the first selector circuit and the second selector circuit;
• and
• a first multiplexor circuit configured to selectively couple the first bus to the first bias node;
• a second decoder module coupled to the memory array, the second decoder disposed adjacent a first boundary of the first decoder module, the second decoder module comprising:
• a second word line decoder comprising a third selector circuit;
• a second bit line decoder comprising a fourth selector circuit;
• a third bus coupled to the first bias node, the third selector circuit and the fourth selector circuit;
• a fourth bus coupled to the second bias node, the third selector circuit and the fourth selector circuit;
• and
• a second multiplexor circuit configured to selectively couple the second bus to the second bias node,
• wherein the first bus and the second bus are each coupled to the third selector circuit and the fourth selector circuit and
• wherein the first multiplexor circuit and the second multiplexor circuit are configured to selectively drive the second word line decoder and the second bit line decoder.

A method comprising:

• simultaneously programming a first non-volatile memory cell and a second non-volatile memory cell, the first non-volatile memory cell coupled to a first bit line decoder of a first decoder module, the second non-volatile memory cell coupled to a first word line decoder of the first decoder module and a second decoder module adjacent the first decoder module, the first decoder module comprising a first multiplexor circuit coupled to a positive bias node and a first bus, the second decoder module comprising a second multiplexor circuit coupled to the positive bias node and a second bus, by:
• selectively coupling the first multiplexor circuit via the first bus to the first bit line decoder;
• and
• selectively coupling the second multiplexor circuit via the second bus to the first word line decoder,
• wherein:
• the second bus extends outside a boundary of a second decoder circuit into a boundary of a first decoder circuit;
• and
• the first non-volatile memory cell and the second non-volatile memory cell each are programmed using positive and negative voltages.