Breakdown mitigation for programmable resistance memory element

A memory system comprising:

• a cross-bar array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of programmable resistance memory cells, each programmable resistance memory cell having a threshold switching selector in series with a programmable resistance memory element, each programmable resistance memory cell located at a cross-point between one of the first conductive lines and one of the second conductive lines;
• a decoder circuit comprising a transistor having a control gate;
• and
• one or more control circuits in communication with the cross-bar array and with the decoder circuit, the one or more control circuits configured to:
• apply a first voltage to the control gate of the transistor to cause the transistor to have a first resistance while the transistor delivers a first current to a selected first conductive line in the cross-bar array to charge a voltage on the selected first conductive line during a forming operation of a threshold switching selector in a selected programmable resistance memory cell connected to the selected first conductive line;
• and
• apply a second voltage to the control gate of the transistor to cause the transistor to have a second resistance while the transistor delivers a second current to the selected first conductive line in the cross-bar array to charge a voltage on the selected first conductive line during a read operation of the selected programmable resistance memory cell connected to the selected first conductive line, wherein the second resistance is less than the first resistance.