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US 12,718,759 B2Granted
Display device
AssigneeSamsung Display Co., Ltd.
InventorsHaemin Kim, Youngwan Seo, Geunho Lee
Life of this patent
Estimating the term…
Abstract
A display device includes a display area and a peripheral area surrounding the display area, a pixel disposed in the display area on a substrate, an insulating layer disposed on the substrate and having a valley part along a periphery of the display area in the peripheral area, and an emission driver disposed in the peripheral area on the substrate, providing an emission signal to the pixel through an emission line, and overlapping both a first inner surface and a second inner surface of the insulating layer of the valley part in a plan view.
Claims20
A display device comprising:
- a display area and a peripheral area adjacent to the display area;
- a pixel disposed in the display area on a substrate;
- an insulating layer disposed on the substrate and having a valley part along a periphery of the display area in the peripheral area;
- and
- an emission driver disposed in the peripheral area on the substrate, providing an emission signal to the pixel through an emission line, overlapping both a first inner surface and a second inner surface of the insulating layer of the valley part in a plan view, and including stages, wherein
- each of the stages includes a logic circuit part and a buffer circuit part, and
- the first inner surface and the second inner surface of the insulating layer are disposed between the logic circuit part and the buffer circuit part in a plan view.
4 more elements
A display device comprising:
- a display area and a peripheral area adjacent to the display area;
- a pixel disposed in the display area on a substrate;
- an insulating layer disposed on the substrate and having a valley part along a periphery of the display area in the peripheral area;
- and
- a scan driver disposed in the peripheral area on the substrate, providing a scan signal to the pixel through a scan line, overlapping both a first inner surface and a second inner surface of the insulating layer defining the valley part in a plan view, and including stages, wherein
- each of the stages includes a logic circuit part and a buffer circuit part, and
- the first inner surface and the second inner surface of the insulating layer are disposed between the logic circuit part and the buffer circuit part in a plan view.
4 more elements
Dependencies are inferred from the claim text.