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US 12,718,748 B2Granted
Gate driver and electronic device
AssigneeSamsung Display Co., Ltd.
InventorsJaesang Kim, Seongjoo Lee, Ohjo Kwon
Life of this patent
Estimating the term…
Abstract
A gate driver includes a plurality of stages. At least one stage of the plurality of stages includes a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing a logic operation on an output enable signal, the intermediate carry signal and the carry output signal, a level shifting circuit configured to generate a gate signal by shifting a voltage level of the intermediate gate signal, and a buffer circuit configured to output the gate signal at a gate output node when a high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.
Claims20
A gate driver including a plurality of stages, at least one stage of the plurality of stages comprising:
- a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing a logic operation on an output enable signal, the intermediate carry signal and the carry output signal;
- a level shifting circuit configured to generate a gate signal by shifting a voltage level of the intermediate gate signal;
- and
- a buffer circuit configured to output the gate signal at a gate output node when a high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.
1 more element
An electronic device comprising:
- a processor configured to provide input image data;
- and
- a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising:
- a display panel including a plurality of gate lines, and a plurality of pixels connected to the plurality of gate lines;
- a data driver configured to provide data signals to the plurality of pixels;
- a first gate driver arranged on a first side of the plurality of pixels, and configured to provide gate signals to the plurality of pixels through the plurality of gate lines;
- a second gate driver arranged on a second side of the plurality of pixels opposite to the first side, and configured to provide the gate signals to the plurality of pixels through the plurality of gate lines;
- and
- a controller configured to provide a start signal, a clock signal, an output enable signal and a first high impedance signal to the first gate driver, and to provide the start signal, the clock signal, the output enable signal and a second high impedance signal to the second gate driver,
- wherein the first gate driver includes a plurality of first stages, the second gate driver includes a plurality of second stages, and
- at least one stage among the plurality of first stages and the plurality of second stages includes:
- a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on the clock signal, and to generate an intermediate gate signal by performing a logic operation on the output enable signal, the intermediate carry signal and the carry output signal;
- a level shifting circuit configured to generate a gate signal corresponding to one of the gate signals by shifting a voltage level of the intermediate gate signal;
- and
- a buffer circuit configured to output the gate signal at a gate output node when a high impedance signal corresponding to one of the first high impedance signal and the second high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.
12 more elements
An electronic device comprising:
- a processor configured to provide input image data;
- and
- a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising:
- a display panel including a plurality of write lines, a plurality of compensation lines, a plurality of first initialization lines, a plurality of second initialization lines, a plurality of anode initialization lines, a plurality of emission lines and a plurality of pixels;
- a data driver configured to provide data signals to the plurality of pixels;
- left and right write drivers arranged on left and right sides of the plurality of pixels, respectively, and configured to provide write signals to the plurality of pixels through the plurality of write lines;
- left and right compensation drivers arranged on the left and right sides of the plurality of pixels, respectively, and configured to provide compensation signals to the plurality of pixels through the plurality of compensation lines;
- left and right first initialization drivers arranged on the left and right sides of the plurality of pixels, respectively, and configured to provide first initialization signals to the plurality of pixels through the plurality of first initialization lines;
- left and right second initialization drivers arranged on the left and right sides of the plurality of pixels, respectively, and configured to provide second initialization signals to the plurality of pixels through the plurality of second initialization lines;
- left and right anode initialization drivers arranged on the left and right sides of the plurality of pixels, respectively, and configured to provide anode initialization signals to the plurality of pixels through the plurality of anode initialization lines;
- left and right emission drivers arranged on the left and right sides of the plurality of pixels, respectively, and configured to provide emission signals to the plurality of pixels through the plurality of emission lines;
- and
- a controller configured to provide a same clock signal to the left and right write drivers, the left and right compensation drivers, the left and right first initialization drivers, the left and right second initialization drivers, the left and right anode initialization drivers, and the left and right emission drivers, to provide left and right write high impedance signals to the left and right write drivers, respectively, to provide left and right compensation high impedance signals to the left and right compensation drivers, respectively, to provide left and right first initialization high impedance signals to the left and right first initialization drivers, respectively, to provide left and right second initialization high impedance signals to the left and right second initialization drivers, respectively, to provide left and right anode initialization high impedance signals to the left and right anode initialization drivers, respectively, and to provide left and right emission high impedance signals to the left and right emission drivers, respectively,
- wherein each of the left and right write drivers, the left and right compensation drivers, the left and right first initialization drivers, the left and right second initialization drivers, the left and right anode initialization drivers, and the left and right emission drivers includes a plurality of stages, and
- wherein at least one stage of the plurality of stages includes:
- a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on the clock signal, and to generate an intermediate gate signal by performing a logic operation on the output enable signal, the intermediate carry signal and the carry output signal;
- a level shifting circuit configured to generate a gate signal corresponding to one of the write signals, the compensation signals, the first initialization signals, the second initialization signals, the anode initialization signals and the emission signals by shifting a voltage level of the intermediate gate signal;
- and
- a buffer circuit configured to output the gate signal at a gate output node when a high impedance signal corresponding to one of the left and right write high impedance signals, the left and right compensation high impedance signals, the left and right first initialization high impedance signals, the left and right second initialization high impedance signals, the left and right anode initialization high impedance signals, and the left and right emission high impedance signals has a first level, and to float the gate output node when the high impedance signal has a second level.
16 more elements
Dependencies are inferred from the claim text.