Gate drive circuit and display panel

A display panel, comprising:

• a plurality of pixel circuits each comprising a write transistor configured to control input of a data signal and a compensation transistor configured to control input of the data signal to a gate of a drive transistor;
• and
• a gate drive circuit comprising a plurality of shift registers, each of the plurality of shift registers comprising:
• a cascade transmission signal selection sub-circuit electrically connected between a first wire and a first node;
• a pull-up control module configured to control a potential of a second node based on a potential of the first node and a potential of a first clock signal:
• a pulse quantity reduction sub-circuit electrically connected between the second node and a third node, wherein a control terminal of the pulse quantity reduction sub-circuit is electrically connected to a reset line;
• a first inverting sub-circuit connected between the second node and a fourth node;
• a first output module configured to output a first gate drive signal based on a potential of the third node and a potential of the fourth node:
• a second output module comprising a first transistor of P-channel and a second transistor of N-channel, wherein a first electrode of the first transistor is electrically connected to a high potential line, a gate of the first transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to a second electrode of the first transistor to output a second gate drive signal, and a gate of the second transistor is electrically connected to the gate of the first transistor;
• and
• a voltage boosting sub-circuit connected in series between a second electrode of the second transistor and a low potential line, wherein a control terminal of the voltage boosting sub-circuit is electrically connected to the gate of the second transistor,
• wherein an output terminal of the first output module is electrically connected to a gate of the write transistor, and an output terminal of the second output module is electrically connected to a gate of the compensation transistor.