Apparatus with in-memory processing using systolic arrays and computing apparatus including the same

An apparatus, the apparatus comprising:

• a convolution operation data path circuitry, connected to a global memory storing input feature map (IFM) data, weights, kernel data, and output feature map (OFM) data, comprising:
• an IFM fetcher circuitry, connected to the global memory, configured to form an IFM vector stream comprising at least two IFM vectors from the IFM data;
• a kernel fetcher circuitry, connected to the global memory, configured to form a kernel vector stream comprising at least two kernel vectors from the kernel data;
• a systolic array comprising a plurality of processing elements (PEs) and is configured to receive the IFM vector stream and the kernel vector stream;
• and
• an OFM write-back circuitry configured to write a plurality of OFMs to the global memory,
• wherein each of the plurality of PEs comprises a plurality of vector circuitries,
• wherein each of the plurality of vector circuitries comprises a collection of multiplier hardware and an adder tree and each of the plurality of the vector circuitries is configured to, per unit clock cycle, perform a complete dot-product operation on an IFM vector of the IFM vector stream and a kernel vector of the kernel vector stream, each PE generates at least two OFM pixels per unit clock cycle by simultaneously performing a plurality of complete dot-product operations is that throughput in parallel processing capability of the systolic array is enabled, and wherein a number of the OPM pixels generated per unit clock cycle of each PE is dependent on a number of vector circuitries available in each PE.