Structure and technique of photo-defined semiconductor device with selective dielectric constant reduction
AssigneeApplied Materials, Inc.
InventorBenjamin D. Briggs
Life of this patent
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Abstract
A semiconductor device may include a substrate. The semiconductor device may also include a dielectric material characterized, at least in part, by a dielectric constant. The semiconductor device may include a metallic pathway formed in the dielectric material. The semiconductor device may include a region about the metallic pathway of the semiconductor device may include a plurality of air gaps within the dielectric material and arranged three-dimensionally throughout the region, where the region may include a lower dielectric constant than the dielectric constant of the dielectric material.
Claims19
A method of constructing a redistribution layer of a semiconductor device, the method comprising:
- identifying, by a computing device, a three-dimensional region of the semiconductor device where a pathway may be formed, wherein a material to be used to manufacture the semiconductor device comprises a dielectric constant, and a desired signal integrity along the pathway requires a lower dielectric constant;
- generating, by the computing device, a deposition plan characterized by air gaps formed in the three-dimensional region of the semiconductor device where the pathway may be formed;
- determining, by the computing device, that the deposition plan at least meets mechanical properties limits associated with the three-dimensional region of the semiconductor device;
- and
- in response to determining that the deposition plan at least meets the mechanical properties limits associated with the three-dimensional region of the semiconductor device:
- providing, by the computing device, the deposition plan to a semiconductor processing system such that the semiconductor processing system executes the deposition plan and forms the semiconductor device comprising the pathway through the three-dimensional region, the three-dimensional region characterized by the lower dielectric constant such that the desired signal integrity is achieved.
A system comprising:
- a semiconductor processing chamber, configured to receive a substrate;
- a lithography tool configured to perform 2-photon lithography;
- and
- a computing device comprising:
- one or more processors;
- and
- a non-transitory computer-readable medium comprising instructions, that, when executed by the one or more processors, cause the computing device to perform operations to:
- identify a three-dimensional region of a semiconductor device where a pathway may be formed, wherein a material to be used to manufacture the semiconductor device comprises a dielectric constant and a desired signal integrity along the pathway requires a lower dielectric constant;
- generate a deposition plan characterized by air gaps formed in the three-dimensional region of the semiconductor device where the pathway may be formed;
- determine that the deposition plan at least meets mechanical properties limits associated with the three-dimensional region of the semiconductor device;
- and
- in response to determining that the deposition plan at least meets the mechanical properties limits associated with the three-dimensional region of the semiconductor device:
- provide the deposition plan to a semiconductor processing system such that the semiconductor processing system executes the deposition plan and forms the semiconductor device comprising the pathway through the three-dimensional region, the three-dimensional region characterized by the lower dielectric constant such that the desired signal integrity is achieved.
Dependencies are inferred from the claim text.