Inline cryptographic engine for storage controllers

One or more processors, configured to:

• receive a cryptographic core configuration request for a data stream of a multi-data stream memory controller, wherein each data stream comprises:
• encrypted data to be written to a non-volatile storage memory;
• or
• decrypted data to be written to a random access memory (RAM) or a cache memory associated with a system on chip (SoC);
• activate first cryptographic core for encryption or decryption of data associated with the data stream;
• allocate the first cryptographic core to the data stream;
• and
• point a stream current pointer to the first cryptographic core based on the allocating the first cryptographic core, wherein the stream current pointer indicates that a new incoming data block is assigned to the first cryptographic core.

A computing device, comprising:

• means for receiving a cryptographic core configuration request for a data stream of a multi-data stream memory controller, wherein each data stream comprises:
• encrypted data to be written to a non-volatile storage memory;
• or
• decrypted data to be written to a random access memory (RAM) or a cache memory associated with a system on chip (SoC);
• means for activating a first cryptographic core for encryption or decryption of data associated with the data stream;
• means for allocating the first cryptographic core to the data stream;
• and
• means for pointing a stream current pointer to the first cryptographic core based on the allocating the first cryptographic core, wherein the stream current pointer indicates that a new incoming data block is assigned to the first cryptographic core.