Rotating accumulator
AssigneeXmos Ltd
InventorHendkik Lambertus Muller
Life of this patent
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Abstract
A processing unit for generating an output vector is provided. The processing unit comprises an output vector register and a vector unit and is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit. The instruction set includes a vector processing instruction defined by a corresponding opcode, which causes the processing unit to: i) process, using the vector unit, at least two input vectors to generate a result value; ii) perform a rotation operation on the plurality of elements of the output register in which the result value or a value based on the result value is placed in the first end element of the output register.
Claims12
A processing unit for generating an output vector, the processing unit comprising:
- an output register having a plurality of elements for holding different components of the output vector, the plurality of elements including a first end element and a second end element;
- and
- a vector unit for processing at least two input vectors to generate respective result values;
- wherein the processing unit is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit, wherein the instruction set includes a vector processing instruction defined by a corresponding opcode, the vector processing instruction causing the processing unit to perform operations of:
- processing, using the vector unit, a first input vector and a second input vector to generate a result value;
- and
- performing a rotation operation on the plurality of elements of the output register in which the sum of the result value and a value present in the second end element before said rotation is placed in the first end element of the output register.
A method, performed by a processing unit, of generating an output vector at an output register having a plurality of elements for holding different components of the output vector, the plurality of elements including a first end element and a second end element, wherein the processing unit is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit, wherein the instruction set includes a vector processing instruction defined by a corresponding opcode, the method comprising the vector processing instruction causing the processing unit to implement a vector processing operation of:
- processing, using the vector unit, a first input vector and a second input vector to generate a result value;
- and
- performing a rotation operation on the plurality of elements of the output register in which the sum of the result value and a value present in the second end element before said rotation is placed in the first end element of the output register.
Dependencies are inferred from the claim text.