Direct memory access systems

A system comprising:

• an accelerator, and
• at least one processor comprising one or more circuits to;
• obtain an instruction to be performed by the accelerator;
• determine the one or more operations to be performed by the accelerator based at least on (i) the instruction, (ii) a datapath associated with the accelerator, and (iii) determining the one or more operations are compatible operations that the accelerator is configured to execute, the datapath representing one or more transfers of data within the accelerator via one or more components of the accelerator, the data having a datatype that is compatible with the accelerator;
• generate a set of accelerator instructions in an instruction set architecture (ISA) of the accelerator based at least on the one or more operations to be performed by the accelerator;
• and
• provide the data associated with the set of accelerator instructions to cause the accelerator to operate in accordance with the set of accelerator instructions.

A method comprising:

• obtaining an instruction to be performed by an accelerator;
• determining the one or more operations to be performed by the accelerator based at least on (i) the instruction, (ii) a datapath associated with the accelerator, and (iii) determining the one or more operations are compatible operations that the accelerator is configured to execute, the datapath representing one or more transfers of data within the accelerator via one or more components of the accelerator, and the data having a datatype that is compatible with the accelerator;
• generating a set of accelerator instructions in an instruction set architecture (ISA) of the accelerator based at least on the one or more operations to be performed by the accelerator;
• and
• providing data associated with the set of accelerator instructions to a system to cause the system to coordinate operation of the accelerator in accordance with the set of accelerator instructions.