US 12,717,748 B2Granted

Data communication system and slave device

AssigneeLAPIS Technology Co., Ltd.

InventorKunihiro Harayama

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Abstract

A master device transmits a clock signal to a first slave device together with a write data signal including write data pieces respectively corresponding to slave devices connected in cascade. Each slave device includes a buffer that receives the clock signal, outputs an amplified clock signal, and transmits the clock signal to a next stage slave device, and an information acquisition circuit that acquires information data pieces and reads them as read data pieces. The slave devices take in a series of write data pieces included in the write data signal while shifting them at the timing of the clock signal output from each of the master device and the buffer and transmit a read data signal including a series of read data pieces read from each information acquisition circuit to the master device via the first slave device while shifting them at the timing of the clock signal group.

Claims18

Dependent claims

A data communication system comprising:

a master device;
a first slave device connected to the master device;
and
a second to N-th slave devices cascade-connected to the first slave device, N being an integer of 2 or more,
wherein the master device and the adjacent devices of the first to N-th slave devices are connected by at least three wires including a wire for transmitting a clock signal, a wire for transmitting a write data signal, and a wire for transmitting a read data signal,
wherein the master device executes a write operation of transmitting as the write data signal a signal including a series of first to N-th write data pieces respectively taken into the first to N-th slave devices to the first slave device within a predetermined period,
wherein the clock signal is sequentially transmitted from the master device to the first to N-th slave devices and is responsible for a timing of transmitting or receiving the write data signal and the read data signal in each of the first to N-th slave devices,
wherein the first to N-th slave devices take in a write data piece corresponding to itself from the write data signal received from a front stage device based on the clock signal received from the front stage device, transmit as the write data signal a signal including a series of write data piece obtained by excluding the taken write data piece to a rear stage device, and transmit as the read data signal a signal including a series of read data pieces obtained by adding a read data piece acquired within itself to the read data signal received from the rear stage device to the front stage device, and
wherein the master device further executes a read operation of receiving the read data signal including a series of first to N-th read data pieces respectively acquired from the first to N-th slave devices from the first slave device within the predetermined period.

6 more elements

A slave device comprising:

a first input terminal for receiving a write data signal;
a second input terminal for receiving a read data signal;
a third input terminal for receiving a clock signal;
a first to third output terminals;
a write data transmission/reception circuit that outputs the write data signal received at the first input terminal from the first output terminal at a timing of the clock signal received at the third input terminal;
and
a read data transmission/reception circuit that outputs the read data signal received at the second input terminal from the second output terminal at the timing of the clock signal received at the third input terminal,
wherein the clock signal received at the third input terminal is internally transmitted and output from the third output terminal,
wherein the write data transmission/reception circuit executes a write operation of taking in a write data piece corresponding to itself from a series of write data pieces consisting of at least one write data piece included in the write data signal received at the first input terminal and outputting a write data signal including a series of write data pieces obtained by excluding the taken write data piece from the first output terminal at the timing of the clock signal received at the third input terminal within a predetermined period, and
wherein the read data transmission/reception circuit executes a read operation of outputting a read data signal including an information data piece acquired within itself as a read data piece in the read data signal received at the second input terminal from the second output terminal at the timing of the clock signal received at the third input terminal within the predetermined period.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/660,191Filed 9 May 2024
Priority: JP 2023-07849511 May 2023
Published: US 2024/0378169 A114 Nov 2024
Granted: 25 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 13/4247
Bus transfer protocol, e.g. handshake; Synchronisation: on a daisy chain bus
G06F 13/4282
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
G06F 2213/40
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central…:…
G06F
Computing and data processing