Scalable address decoding scheme for CXL Type-2 devices with programmable interleave granularity
AssigneeIntel Corporation
InventorsAnand K. Enamandram, Ritu Gupta
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Abstract
Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.
Claims20
An apparatus comprising:
- configurator logic circuitry to determine an interleave granularity and an address range size for a plurality of devices of a type coupled to a socket of a processor, wherein the configurator logic circuitry is to determine the interleave granularity based on a size of a Largest sized device from the plurality of devices;
- a memory to store a single System Address Decoder (SAD) rule for two or more of the plurality of the devices of a type coupled to the socket of the processor, wherein the SAD rule maps an aggregate memory size required by all devices of the type in the socket and interleaves the devices using higher order physical address bits;
- wherein a memory access transaction directed at a first device from the plurality of devices is to be routed to the first device in accordance with the SAD rule, wherein the configurator logic circuitry is to operate at boot time in accordance with information from one of:
- a Basic Input Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), and a Baseboard Management Controller (BMC) firmware.
A system comprising:
- a processor;
- a plurality of devices of a type coupled to a socket the processor;
- configurator logic circuitry to determine an interleave granularity and an address range size for the plurality of devices of the type coupled to the socket of the processor, wherein the configurator logic circuitry is to determine the interleave granularity based on a size of a largest sized device from the plurality of devices;
- a memory to store a single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor, wherein the SAD rule maps an aggregate memory size required by all devices of the type in the socket and interleaves the devices using higher order physical address bits;
- wherein a memory access transaction directed at a first device from the plurality of devices is to be routed to the first device in accordance with the SAD rule, wherein the configurator logic circuitry is to operate at boot time in accordance with information from one of:
- a Basic Input Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), and a Baseboard Management Controller (BMC) firmware.
Dependencies are inferred from the claim text.