Round robin bus arbitration with control vectors and increment and decrement functions

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a plurality of bus requesters, wherein the plurality of bus requesters is coupled to a common bus by an arbitration logic;
• requesting, by at least one bus requester, access to the common bus, wherein the requesting is stored in a request vector (RV);
• checking a grant history vector (GHV), wherein the GHV indicates a last granted requester within the plurality of bus requesters;
• creating a relative request vector (RRV), wherein the creating includes performing one or more circular shifts on the RV, wherein the last granted requester does not occupy a first bit position within the RV, wherein a direction of the one or more circular shifts is in a right direction, wherein N represents a number of circular shifts performed;
• examining a first asserted bit within the RRV, wherein the examining begins at a second bit position within the RRV, wherein the examining proceeds in a first direction;
• generating a relative grant vector (RGV), wherein the RGV is based on the first asserted bit within the RRV, wherein the RGV comprises a one-hot encoding;
• producing a grant vector (GV), wherein the producing includes executing N circular shifts of the RGV, wherein a direction of the executing N circular shifts is in a left direction;
• and
• granting access, by the arbitration logic, of the common bus to a bus requester indicated by the GV.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a plurality of bus requesters, wherein the plurality of bus requesters is coupled to a common bus by an arbitration logic;
• request, by at least one bus requester, access to the common bus, wherein the requesting is stored in a request vector (RV);
• check a grant history vector (GHV), wherein the GHV indicates a last granted requester within the plurality of bus requesters;
• create a relative request vector (RRV), wherein the creating includes performing one or more circular shifts on the RV, wherein the last granted requester does not occupy a first bit position within the RV, wherein a direction of the one or more circular shifts is in a right direction, wherein N represents a number of circular shifts performed;
• examine a first asserted bit within the RRV, wherein the examining begins at a second bit position within the RRV, wherein the examining proceeds in a first direction;
• generate a relative grant vector (RGV), wherein the RGV is based on the first asserted bit within the RRV, wherein the RGV comprises a one-hot encoding;
• produce a grant vector (GV), wherein the producing includes executing N circular shifts of the RGV, wherein a direction of the executing N circular shifts is in a left direction;
• and
• grant access, by the arbitration logic, of the common bus to a bus requester indicated by the GV.