Communication system with improved signal delay and slave device and operating method thereof
AssigneePixart Imaging Inc.
InventorYen-Hsiang Chew
Life of this patent
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Abstract
There is provided a communication system including a master device and a slave device. The master device includes a first interface port and a second interface port. When the master device runs a read operation, the first interface port is used to output a serial clock to the slave device. The slave device includes a clock generator used to generate a delayed serial clock having the same phase as read data according to the serial clock. The second interface port is used to receive the delayed serial clock and the read data to eliminate a time delay in a data transaction.
Claims18
A communication system, comprising:
- a master device, comprising a first interface port and a second interface port;
- and
- a slave device, configured to
- receive a serial clock (SCLK) from the first interface port via a first SCLK line, and
- output a delayed SCLK of the SCLK to the second interface port via a second SCLK line;
- wherein the slave device comprises a clock generator configured to generate the delayed SCLK, and the clock generator comprises:
- a first flip flop, an input terminal thereof connected to a shift register of the slave device, a clock input thereof configured to receive a reverse signal of the SCLK, and an output terminal thereof configured to output read data;
- a second flip flop, an output terminal thereof connected to an input terminal thereof via a first NOT gate, and a clock input thereof configured to receive a reverse signal of the SCLK:
- a third flip flop, an output terminal thereof connected to an input terminal thereof via a second NOT gate, and a clock input thereof configured to receive the SCLK;
- and
- an XNOR gate, directly connected to the output terminal of the second flip flop and the third flip flop to output the delayed SCLK.
A slave device adopting an SPI, the slave device comprising:
- a first SCLK pin, configured to receive an SCLK;
- a clock generator, configured to generate a delayed SCLK of the SCLK, wherein the clock generator comprises:
- a first flip flop, an input terminal thereof connected to a shift register of the slave device, a clock input thereof configured to receive a reverse signal of the SCLK, and an output terminal thereof configured to output the read data;
- a second flip flop, an output terminal thereof connected to an input terminal thereof via a first NOT gate, and a clock input thereof configured to receive a reverse signal of the SCLK;
- a third flip flop, an output terminal thereof connected to an input terminal thereof via a second NOT gate, and a clock input thereof configured to receive the SCLK;
- and
- an XNOR gate, directly connected to the output terminal of the second flip flop and the third flip flop to output the delayed SCLK;
- a second SCLK pin, configured to output the delayed SCLK;
- and
- a master-in-slave-out (MISO) pin, configured to output read data to a master device.
An operating method of a communication system adopting an SPI, the communication system comprising a master device and a slave device, the operating method comprising:
- receiving, by the slave device, address data via a master-out-slave-in (MOSI) line and an SCLK via an SCLK line from the master device;
- upon identifying the address data indicating a read operation, outputting, by a clock generator of the slave device, a delayed SCLK of the SCLK to the master device, wherein the clock generator comprises:
- a first flip flop, an input terminal thereof connected to a shift register of the slave device, a clock input thereof configured to receive a reverse signal of the SCLK, and an output terminal thereof configured to output the read data;
- a second flip flop, an output terminal thereof connected to an input terminal thereof via a first NOT gate, and a clock input thereof configured to receive a reverse signal of the SCLK;
- a third flip flop, an output terminal thereof connected to an input terminal thereof via a second NOT gate, and a clock input thereof configured to receive the SCLK;
- and
- an XNOR gate, directly connected to the output terminal of the second flip flop and the third flip flop to output the delayed SCLK;
- and
- upon identifying the address data indicating a write operation, stopping outputting the delayed SCLK by the clock generator.
Dependencies are inferred from the claim text.