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US 12,717,734 B2Granted
Delay elements for command timing in a memory device
AssigneeMicron Technology, Inc.
InventorsJames S. Rehmeyer, Christopher G. Wieduwilt
Life of this patent
Estimating the term…
Abstract
A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.
Claims20
A method, comprising:
- receiving, via a shared command bus, a command at each memory device of a plurality of memory devices, wherein each of the memory devices comprises:
- a plurality of delay elements configured to alter a timing of a decoded command relative to other of the plurality of memory devices,
- at least one memory array, and
- at least one decoder;
- decoding the command at each of the memory devices utilizing at least one decoder associated with each of the memory devices to generate the decoded command for each of the memory devices;
- receiving a delay trim input representing latched fuse states;
- selecting a portion of the plurality of delay elements;
- receiving the decoded command at the portion of the plurality of delay elements of each of the memory devices;
- and
- receiving the decoded command at the memory arrays of each of the memory devices through respective command paths of each of the memory devices configured utilizing the respective delay trim input used to select the portion of the plurality of delay elements of each of the memory devices.
7 more elements
An apparatus, comprising:
- an array of memory cells;
- delay elements;
- selector blocks coupled to the delay elements;
- and
- a decoder coupled to the array of memory cells and the delay elements, wherein the decoder is configured to decode a command to generate a decoded command comprising at least one of an activate command and a precharge command for the array;
- wherein the selector blocks are configured to:
- receive a delay trim input representing latched fuse states;
- and
- select a portion of the delay elements based on the delay trim input;
- wherein the portion of the delay elements are configured to:
- receive the decoded command;
- and
- alter a timing of an implementation of the decoded command at the array as compared to different timings of an implementation of the decoded command by different apparatuses that share a command bus.
10 more elements
An apparatus, comprising:
- a programming module configured to:
- receive an execution order corresponding to a plurality of memory devices of a memory system, wherein each of the memory devices comprises delay elements and a memory array and wherein each of the memory devices shares a command bus from the memory system;
- responsive to receipt of the execution order, select a portion of the delay elements using selector blocks based on a received delay trim input representing latched fuse states;
- and
- program each of the delay elements differently such that a command path internal to the memory devices has a different delay for each of the memory devices using the portion of the delay elements.
2 more elements
Dependencies are inferred from the claim text.