Bus remapping data protection for volatile memories

A memory system comprising:

• a memory controller;
• a memory;
• and
• a bus coupling the memory controller to the memory, wherein the bus is configured to:
• remap data bits according to a predetermined remapping scheme as the data bits are transmitted from the memory controller to the memory, and
• inverse remap the data bits according to an inverse of the predetermined remapping scheme, as the data bits are transmitted from the memory to the memory controller, to restore the original order of the data bits, wherein the predetermined remapping scheme comprises a multiplexing factor scheme that separates initially adjacent bits by a number of bit positions equal to a multiplexing factor of the multiplexing factor scheme.

A method for operating a memory system, the method comprising:

• receiving, at a memory controller, data bits for a word to be stored in a memory;
• remapping, by the memory controller, the data bits according to a predetermined remapping scheme to create remapped data bits, wherein the predetermined remapping scheme comprises a multiplexing factor scheme that separates initially adjacent bits by a number of bit positions equal to a multiplexing factor of the multiplexing factor scheme;
• generating, by the memory controller, parity bits based on the remapped data bits;
• storing the original, unremapped data bits in the memory;
• and
• storing the generated parity bits in the memory.