Method for processing task, processor, device and readable storage medium

A heterogeneous multi-core processor, comprising:

• a dedicated acceleration core, comprising a first on-chip cache inside the dedicated acceleration core and a control unit coupled to the first on-chip cache;
• a general-purpose processing core, comprising a routing structure component and at least one general-purpose processing unit coupled to the routing structure component;
• a data path, comprising a bus configured to directly couple the routing structure component to the first on-chip cache so that the at least one general-purpose processing unit can access the first on-chip cache without passing through any other cache, wherein the routing structure component is only provided in the general-purpose processing core;
• and
• a signal path, configured to couple the at least one general-purpose processing unit to the control unit for transferring an instruction completion indication related to the access;
• the general-purpose processing core further comprising:
• a second on-chip cache inside the general-purpose processing core, coupled to the routing structure component, the routing structure component being configured to access the first on-chip cache via the data path or the second on-chip cache based on received address information.

An electronic device, comprising:

• at least one heterogeneous multi-core processor;
• and
• a memory connected to the at least one heterogeneous multi-core processor, wherein the memory stores one or more computer instructions executable by the at least one heterogeneous multi-core processor, wherein the one or more computer instructions, when executed by the at least one heterogeneous multi-core processor, cause the electronic device to perform operations for processing a computing task by the at least one heterogeneous multi-core processor, the at least one heterogeneous multi-core processor comprising a general-purpose processing core and a dedicated acceleration core, and the operations comprising:
• for a predetermined type of computing task, allocating a plurality of instruction blocks in the computing task to the general-purpose processing core and the dedicated acceleration core;
• transferring, by a control unit in the dedicated acceleration core, an instruction completion indication of a predetermined co-processing unit coupled thereto to at least one processing unit of the general-purpose processing core through a signal path, the signal path being configured to couple the at least one general-purpose processing unit to the control unit;
• and
• in response to determining that the instruction completion indication is received, acquiring, by the general-purpose processing core, data from a first on-chip cache inside the dedicated acceleration core through a data path for completing the computing task, the data path being configured to couple the general-purpose processing core to the first on-chip cache, wherein the data path is a bus directly coupling a routing structure component to the first on-chip cache without coupling any other cache, and the routing structure component is only provided in the general-purpose processing core and is coupled directly to the at least one processing unit of the general-purpose processing core;
• wherein acquiring the data comprises:
• sending an access address for the data to the routing structure component;
• determining, by the routing structure component, to access a second on-chip cache inside the general-purpose processing core or the first on-chip cache based on the access address;
• and
• in response to determining to access the first on-chip cache, acquiring the data from the access address in the first on-chip cache via the data path.