Network-attached hostless accelerator devices
AssigneeAdvanced Micro Devices, Inc.
InventorMazda Sabony
Life of this patent
Estimating the term…
Abstract
A processing system includes one or more network-attached hostless accelerator (NAHA) units each having an integrated circuit. The integrated circuit of each NAHA unit includes a memory and a first network interface controller configured to communicatively couple the memory to a network such that the memory of the NAHA unit is communicatively coupled to one or more memories of other NAHA units via the network. Additionally, a NAHA unit of the processing system includes one or more processor cores configured to execute an instruction to generate a result. Further, the one or more processor cores of the NAHA unit are configured to store the result in the one or more memories of the other NAHA units.
Claims20
A network-attached hostless accelerator (NAHA) unit, comprising:
- an integrated circuit comprising:
- a first memory disposed on a same die as a first network interface controller (NIC) configured to communicatively couple the first memory to a first network;
- a cache including a second NIC configured to communicatively couple the cache to a second network;
- and
- one or more processor cores, wherein at least one processor core of the one or more processor cores is configured to:
- execute one or more instructions to generate a first result and a second result;
- store, via the first NIC, the first result in a second memory communicatively coupled to the first network;
- and
- store, via the second NIC, the second result in a second cache communicatively coupled to the second network.
A method, comprising:
- communicatively coupling, by a first network interface controller (NIC) of an integrated circuit, a cache of the integrated circuit to a first network;
- communicatively coupling, by a second NIC of the integrated circuit, a memory of the integrated circuit to a second network;
- executing, by the integrated circuit, a first instruction to generate a first result and a second instruction to generate a second result;
- storing, via the first NIC, the first result in a second cache communicatively coupled to the first network;
- and
- storing, via the second NIC, the second result in a second memory communicatively coupled to the second network.
A processing system, comprising:
- a cache network;
- a first network-attached hostless accelerator (NAHA) unit including a first integrated circuit comprising:
- a first cache;
- a first network interface controller (NIC) included in the first cache and configured to communicatively couple the first cache to the cache network;
- and
- one or more processor cores;
- and
- a second NAHA unit including a second integrated circuit comprising:
- a second cache;
- a second NIC included in the second cache and configured to communicatively couple the second cache to the cache network;
- and
- one or more processor cores configured to:
- execute an instruction to generate a result;
- and
- store, by the second NIC, the result in the first cache of the first NAHA.
Dependencies are inferred from the claim text.