Dynamically adjusting thread affinitization using hardware-based core availability notifications

At least one computer readable medium comprising instructions, which when executed by a processor, cause the processor to execute a method comprising:

• receiving, via an interface, an indication that one or more cores of a processor are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled to the one or more cores, wherein a first core of the one or more cores, when in the forced idle state, is to execute an affinitized workload in a non-performant manner;
• updating a core status structure to identify the one or more cores to be in the forced idle state;
• and
• notifying at least one application regarding the updating of the core status structure.

A system comprising:

• a system on chip (SoC) comprising:
• a first plurality of cores to execute instructions;
• a second plurality of cores to execute instructions;
• a power controller to control delivery of an operating voltage and an operating frequency to the first plurality of cores and the second plurality of cores;
• a control circuit coupled to the first plurality of cores and the second plurality of cores, the control circuit, in response to a constraint in the SoC, to communicate to an operating system (OS) an identification of transition of one or more of at least one of the first plurality of cores or the second plurality of cores to a forced idle state,
• wherein a first core of at least one of the first plurality of cores or the second plurality of cores, when in the forced idle state, is to execute an affinitized thread in a non-performant manner;
• a system memory coupled to the SoC, the system memory to store a hardware feedback interface, the hardware feedback interface comprising efficiency information and performance information of the first plurality of cores and the second plurality of cores, the hardware feedback interface to further indicate a state of the first plurality of cores and the second plurality of cores.