Methods and apparatus to process data packets for logical and virtual switch acceleration in memory

At least one non-transitory computer readable storage medium comprising instructions which cause in-memory compute circuitry to at least:

• read an inbound data packet from an input buffer in memory cells of memory, the inbound data packet from a network, the memory cells including a plurality of input buffers and an a plurality of output buffers to store packets;
• perform at least one virtual switching action on the inbound data packet to determine an outbound data packet without invoking computational resources outside the memory, the at least one virtual switching action implemented based on data included in the instructions, the at least one virtual switching action associated with a packet processing protocol, the at least one virtual switching action to modify a header of the inbound data packet based on the packet processing protocol to determine the outbound data packet;
• output the outbound data packet to an output buffer of the plurality of output buffers in the memory cells of the memory to cause the outbound data packet to be transmitted via the network;
• based on a forwarding table, determine an output address for the outbound data packet to be stored after the at least one virtual switching action is performed, the output address associated with the output buffer of the plurality of output buffers, the forwarding table implemented based on the data included in the instructions;
• and
• based on performance of the at least one virtual switching action, output a control signal to a driver corresponding the output buffer of the memory cells to cause the outbound data packet to be stored at the output address.

A method comprising:

• accessing, with interface circuitry, at least one instruction including data to implement a forwarding table and at least one virtual switching action associated with a virtual switching protocol;
• accessing, with at least one programmable logic circuit in memory, the at least one instruction, the memory including memory cells partitioned into a plurality of input packet buffers and a plurality of output packet buffers to store packets;
• reading, with one or more of the at least one programmable logic circuit, an inbound data packet from an input packet buffer of the plurality of input packet buffers in the memory cells, the inbound data packet from a network;
• performing, with one or more of the at least one programmable logic circuit, the at least one virtual switching action on the inbound data packet to determine an outbound data packet without invoking computational resources outside the memory, the at least one virtual switching action to modify a header of the inbound data packet based on the virtual switching protocol to determine the outbound data packet;
• outputting, with one or more of the at least one programmable logic circuit, the outbound data packet to an output packet buffer of the plurality of output packet buffers in the memory cells, the at least one programmable logic circuit programmed by instructions including the at least one instruction;
• based on the forwarding table, determining, with address generator circuitry, an output address for the outbound data packet to be stored after the virtual switching action is performed, the output address associated with the output packet buffer of the plurality of output packet buffers;
• and
• based on performance of the at least one virtual switching action, outputting, with the address generator circuitry, a control signal to a driver corresponding the output packet buffer of the memory cells to cause the outbound data packet to be stored at the output address.

A memory comprising:

• means for obtaining at least one instruction, the at least one instruction including data to implement a forwarding table and at least one virtual switching action associated with a virtual switching protocol;
• means for storing data, the means for storing data including memory cells including a plurality of input packet buffers and a plurality of output packet buffers to store packets;
• means for processing to be programmed by the at least one instruction, the means for processing to perform the at least one virtual switching action on an inbound data packet to determine an outbound data packet without invoking computational resources outside the memory, the at least one virtual switching action to modify a header of the inbound data packet based on the virtual switching protocol to determine the outbound data packet, the means for processing to:
• access the inbound data packet from an input packet buffer of the plurality of input packet buffers in the means for storing data;
• and
• output the outbound data packet to an output packet buffer of the plurality of output packet buffers in the means for storing data;
• and
• means for determining an output address for the outbound data packet to:
• determine, based on the forwarding table, the output address for the outbound data packet to be stored after the virtual switching action is performed, the output address associated with the output packet buffer of the plurality of output packet buffers;
• and
• based on performance of the at least one virtual switching action, output a control signal to a driver corresponding the output packet buffer of the memory cells to cause the outbound data packet to be stored at the output address.