Memory system and data processing system including the same

A memory system comprising:

• a first chip configured to perform a first operation;
• and
• a stacked memory device configured to include a stacked structure of a plurality of memory cells, the stacked memory device being configured to be accessed by the first chip through a shared bus, and
• a second semiconductor chip including a second body portion, a second through electrode that penetrates the second body portion, and a second connection electrode that is connected to one end of the second through electrode,
• wherein the stacked memory device is disposed over the second semiconductor chip and includes a plurality of first semiconductor chips stacked in a vertical direction, and each of the plurality of first semiconductor chips includes a first body portion, a first through electrode penetrating the first body portion, and a first connection electrode connected to one end of the first through electrode,
• wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes,
• wherein the stacked memory device includes a memory chip, and the second semiconductor chip includes a logic chip for controlling the memory chip.