Predication methods for vector processors
AssigneeTexas Instruments Incorporated
InventorsTimothy Anderson, Duc Quang Bui, Joseph Zbiciak
Life of this patent
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Abstract
A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.
Claims20
A method comprising:
- receiving, by a processor, a predicated instruction including a first field, a second field, and a third field, wherein the first field identifies a predicate register, the second field identifies a condition, and the third field identifies a predication unit for the predicated instruction, and wherein the predication unit is a dedicated predication unit for writing to the predicate register;
- executing, by the processor, the predicated instruction using the predication unit to generate a result;
- and
- storing the result in the predicate register.
A method comprising:
- receiving, by a processor, an execute packet of instructions including:
- a plurality of instructions;
- a first instruction of the plurality of the instructions includes a first field identifying a predication unit for the first instruction;
- a subset of the plurality of instructions, wherein each instruction in the subset of the plurality of instructions includes a second field identifying a functional unit for the instruction;
- and
- a condition code extension instruction including predicate information for the functional units, wherein the predication unit is a dedicated predication unit for updating the predicate information;
- determining, by the processor, the respective functional unit for each instruction of the subset of the plurality of instructions based on the first field;
- executing, by the processor, the first instruction using the predication unit to update the predicate information;
- and
- executing, by the processor, the plurality of instructions using the functional units and using the updated predicate information.
A data processing device comprising:
- a predicate register file;
- a plurality of functional units including a predication unit;
- a memory to store instructions;
- and
- a processing pipeline configurable to execute a packet of instructions fetched from the memory,
- wherein the packet of instructions includes:
- a first instruction;
- a predicated instruction;
- and
- a condition code extension instruction;
- wherein the first instruction includes a first field identifying the predication unit and a second field identifying a predicate register of the predicate register file;
- wherein the predicated instruction includes a field identifying a first functional unit of the plurality of functional units;
- wherein the condition code extension instruction includes a predicate field identifying the predicate register;
- wherein the predication unit is configured to execute the first instruction to update the predicate register;
- wherein the predication unit is a dedicated predication unit for writing to the predicate register;
- wherein each bit in the updated predicate register selects a portion of a first vector or a portion of a second vector;
- and
- wherein the predicate register is associated with the first functional unit of the plurality of functional units.
Dependencies are inferred from the claim text.