System for auto-parallelization of processing codes for multi-processor systems with optimized latency, and method thereof

A compiler system for optimized compiling and auto-parallelization of a program code for execution by a parallel processing system having a plurality of processing units simultaneously processing instructions on data in the parallel processing system by executing the program code, wherein the compiler system comprises means for translating a source program code written in a programming into a machine code as target programming language by generating the machine code as parallel processing code comprising a number of instructions executable by the plurality of processing units of the parallel processing system or controlling the operation of the plurality of processing units;

• wherein the execution of the processing code by the parallel processing system comprises the occurrence of latency times, the latency times being given by idle times of the processing units between transmitting data back to the parallel processing system after having processed a specific block of instructions of the processing code on the data by the processing unit and receiving data necessary for execution of a consecutive block of instructions of the processing code by said processing units,
• wherein the compiler system comprises a parser module for translating the source programming language into a code with a flow of elementary instructions executable by the processing units, the elementary instructions selectable out of a processing-unit-specific set of elementary instructions and the elementary instructions comprising elementary arithmetic operations and/or logic operations and/or control operations and/or memory operations for the number of processing units;
• wherein the parser module comprises means for partitioning the code of elementary instructions into computation block nodes, each computation block node consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code processable by a single processing unit, the smallest possible segmentation of the elementary instructions being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, said sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions, and the read and write instructions needed to receive data required for processing said sequence of elementary instructions by the processing unit and transmit back data after processing by the sequence;
• wherein the compiler system comprises a matrix builder for generating computation and transfer matrices out of computation chains portioned from the code, wherein a computation chain is formed by one or more computation block nodes creating an ordered flow of computation block nodes, wherein each computation chain is executed by one processing unit;
• wherein the computation matrix contains in each row the computation chain of a processing unit with each column having the sequence of elementary instructions of a computation block node within the computation chain of the row and each cell of the transfer matrix contains transfer properties associated with a data transfer from one to a consecutive computation block node, the transfer properties at least comprising what transfers are required at the beginning and at the end of each corresponding cell in the computation matrix;
• and
• wherein the compiler system comprises an optimizer module using an optimization technique by building different combinations of rows from the computation and the transfer matrices, each of the different combinations representing a possible machine code as parallel processing code, and by minimizing an overall occurring latency time as aggregated latency times providing an optimized combination as structure of computational chains being processed by the plurality of processing units, wherein by means of a code generator an optimized machine code is generated for the plurality of processing units of the parallel processing system having a minimized overall latency time.