Tininess detection

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• processing circuitry to perform a processing operation to generate a two's complement result value representing a positive or negative number in two's complement representation;
• normalization-and-rounding circuitry to convert the two's complement result value to a normalized-and-rounded floating-point result value represented using sign-magnitude representation;
• and
• tininess detection circuitry to detect an after-rounding tininess status indicative of whether an outcome of the processing operation is tiny, where a tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the normalized-and-rounded floating-point result value;
• in which:
• the normalization-and-rounding circuitry comprises incrementing circuitry to perform an increment addition to generate a fraction of the normalized-and-rounded floating-point result value, the increment addition comprising one of a result rounding increment for rounding the fraction of the normalized-and-rounded floating-point result value, and a conversion increment for conversion from the two's complement representation to the sign-magnitude representation;
• for an operation where the increment addition is required to be performed by the incrementing circuitry, the tininess detection circuitry is configured to detect the after-rounding tininess status based on a still-to-be-incremented version of the normalized-and-rounded floating-point result value prior to the increment addition by the increment circuitry;
• and
• for an operation where the two's complement result value represents a negative number, the tininess detection circuitry is configured to detect the after-rounding tininess status based on a one's complement value obtained based on inverting bits of the two's complement result value.