Selective multithreaded execution of memory training by central processing unit(CPU) sockets
AssigneeIntel Corporation
InventorJorge Serratos Hernandez
Life of this patent
Estimating the term…
Abstract
Embodiments described herein are generally directed to selective multithreaded execution of memory training by CPU sockets. In an example, a memory configuration and a current phase of execution of memory training for each of multiple CPU sockets of a computer system is received. Based on the memory configuration and the current phase of execution of each of the CPU sockets an estimated power usage across all CPU sockets may be determined. Based on the estimated power usage and a power consumption threshold (e.g., PTAM or PA), performance of the current phase of execution of one or more CPU sockets may be selectively released for one or more channels of the one or more CPU sockets.
Claims20
A non-transitory machine-readable medium storing instructions, which when executed by a processor of a computer system cause the processor to:
- determine an estimated power usage across a plurality of sockets of the computer system based on information regarding a memory configuration of each of the plurality of sockets and information regarding a current phase of execution of memory training for each of the plurality of sockets;
- and
- in accordance with one or more boot processing goals, enabling performance, by one or more sockets of the plurality of sockets, of the current phase of execution for one or more channels of the one or more sockets by selectively releasing performance of the current phase of execution by the one or more sockets based on the estimated power usage and a power consumption threshold.
A method comprising:
- receiving a memory configuration and a current phase of execution of memory training for each of a plurality of central processing unit (CPU) sockets of a computer system;
- determining an estimated power usage across the plurality of CPU sockets based on the memory configuration and the current phase of execution of each of the plurality of CPU sockets;
- and enabling performance, by one or more CPU sockets of the plurality of CPU sockets, of the current phase of execution for one or more channels of the one or more CPU sockets by selectively releasing performance of the current phase of execution by the one or more CPU sockets based on the estimated power usage and a power consumption threshold.
A computer system comprising:
- a boot strap processor (BSP);
- a plurality of sockets;
- and
- instructions that when executed by the BSP cause the BSP to:
- receive a memory configuration and a current phase of execution of memory training for each of the plurality of sockets;
- determine an estimated power usage across the plurality of sockets based on the memory configuration and the current phase of execution of each of the plurality of sockets;
- and
- enabling performance, by one or more CPU sockets of the plurality of CPU sockets, of the current phase of execution for one or more channels of the one or more CPU sockets by releasing performance of the current phase of execution by a subset of the plurality of sockets of the plurality of sockets for one or more channels of the subset of sockets based on the estimated power usage and a power consumption threshold.
Dependencies are inferred from the claim text.