System and method for memory bad block management

A memory system comprising:

• a first interface communicated with a host;
• a plurality of semiconductor memory devices having a first row address, a second row address, a third row address, a fourth row address and a plurality of redundancy rows;
• and
• a memory controller connected to the first interface and configured to control the plurality of semiconductor memory devices,
• wherein the memory controller comprises a remapping table and is configured to:
• allocate the third row address as a first reserved row address and the fourth row address as a second reserved row address;
• generate a first mapping relationship indicating that the first row address is associated with the first reserved row address and a second mapping relationship indicating that the second row address is associated with the second reserved row address;
• store the first mapping relationship and the second mapping relationship in the remapping table;
• and
• remap the first row address to the first reserved row address based on the first mapping relationship and remap the second row address to a second reserved row address based on the second mapping relationship in response to receiving a plurality of host addresses, and
• wherein the first row address and the second row address are not consecutive, and the first reserved row address and the second reserved row address are consecutive.

A memory system comprising:

• a first interface communicated with a host;
• a plurality of semiconductor memory devices having a first normal cell region and a first redundancy region in a first semiconductor memory device, a second normal cell region and a second redundancy region in a second semiconductor memory device which is different from the first semiconductor memory device, and a first reserved region;
• a remapping table configured to store a first information according to a first address, a second information according to a second address;
• and
• a memory controller connected to the first interface and configured to control the plurality of semiconductor memory devices,
• wherein the memory controller is configured to remap the first address to a first target physical address in the first reserved region based on the remapping table and remap the second address to a second target physical address in the first reserved region based on the remapping table in response to a plurality of host addresses, and
• wherein the first target physical address and the second target physical address are consecutive.