US 12,717,487 B2 · Configurable compute-in-memory circuit and method

Abstract

A circuit includes a data buffer configured to sequentially output first and second pluralities of bits, a plurality of memory macros having a total number, and a distribution network coupled between the data buffer and the plurality of memory macros. The distribution network separates the first plurality of bits into the total number of first subsets, and outputs each first subset to a corresponding memory macro, and either outputs an entirety of the second plurality of bits to each memory macro, or separates the second plurality of bits into a number of second subsets less than or equal to the total number, and outputs each second subset to one or more corresponding memory macros. Each memory macro outputs a product of the corresponding first subset and the one of the entirety of the second plurality of bits or the corresponding second subset of the second plurality of bits.

Claims20

Dependent claims

A circuit comprising:

a data buffer configured to sequentially output first and second pluralities of bits;
a plurality of memory macros having a total number of memory macros;
and
a distribution network coupled between the data buffer and the plurality of memory macros, wherein
the distribution network is configured to:
separate the first plurality of bits into the total number of first subsets, and output each first subset to a corresponding memory macro of the plurality of memory macros, and
one of:
output an entirety of the second plurality of bits to each memory macro of the plurality of memory macros, or
separate the second plurality of bits into a number of second subsets less than or equal to the total number, and output each second subset to one or more corresponding memory macros of the plurality of memory macros, and
each memory macro of the plurality of memory macros is configured to output a product of the corresponding first subset and the one of the entirety of the second plurality of bits or the corresponding second subset of the second plurality of bits.

7 more elements

A circuit comprising:

a data buffer configured to sequentially output first and second data elements;
first through fourth memory macros;
and
first through third routing circuits coupled between the data buffer and the first through fourth memory macros,
wherein
the first routing circuit is configured to:
output first and second halves of the first data element to the respective second and third routing circuits, and
output either the second data element to each of the second and third routing circuits, or first and second halves of the second data element to the respective second and third routing circuits,
the second routing circuit is configured to:
output first and second quarters of the first data element to the respective first and second memory macros, and
output either the second data element or the first half of the second data element to each of the first and second memory macros, or first and second quarters of the second data element to the respective first and second memory macros,
the third routing circuit is configured to:
output third and fourth quarters of the first data element to the respective third and fourth memory macros, and
output either the second data element or the second half of the second data element to each of the third and fourth memory macros, or third and fourth quarters of the second data element to the respective third and fourth memory macros, and
each of the first through fourth memory macros is configured to output a product of the corresponding quarter of the first data element and the corresponding second data element, second data element half, or second data element quarter.

12 more elements

A method of operating a circuit, the method comprising:

outputting a first data element from a data buffer to a distribution network, the first data element being one of a weight data element or an input data element;
outputting portions of the first data element from the distribution network to corresponding memory macros of a plurality of memory macros;
outputting a second data element from the data buffer to the distribution network, the second data element being the other of the weight data element or the input data element;
outputting the second data element from the distribution network as one of:
an entirety of the second data element to each memory macro of the plurality of memory macros, or
portions of the second data element to corresponding memory macros of the plurality of memory macros;
and
outputting, from each memory macro of the plurality of memory macros, a product of the corresponding portion of the first data element and the one of the entirety of the second data element or the corresponding portion of the second data element.

5 more elements

Dependencies are inferred from the claim text.

Configurable compute-in-memory circuit and method

Life of this patent

Configurable compute-in-memory circuit and method

Life of this patent

Abstract

Claims20