I/O unit and communication system
AssigneeFanuc Corporation
InventorsMasahiro Saeki, Shinichi Kuwahata, Asunaro Maeda
Life of this patent
Estimating the term…
Abstract
An I/O unit comprises: a plurality of first-stage-side terminals for connecting to a master unit or another I/O unit; a plurality of second-stage-side terminals that are provided in order to connect to the other I/O unit, and are connected to mutually distinct first-stage-side terminals; and a slave process circuit that performs signal processing and is connected to one of the plurality of first-stage-side terminals and to the second-stage-side terminal connected to that first-stage-side terminal.
Claims8
An I/O unit that connects a master unit including a master processing circuit and a device and transmits a signal between the master unit and the device, the I/O unit comprising:
- a plurality of preceding-stage terminals configured to be connected to the master unit provided in a preceding stage of the I/O unit or to another I/O unit provided in the preceding stage;
- a plurality of subsequent-stage terminals configured to be connected to another I/O unit provided in a subsequent stage of the I/O unit, the subsequent-stage terminals being connected respectively to the different preceding-stage terminals;
- and
- a slave processing circuit connected to a first preceding-stage terminal among the plurality of preceding-stage terminals and to a subsequent-stage terminal among the subsequent-stage terminals that is connected to the first preceding-stage terminal, the slave processing circuit being configured to perform signal processing,
- wherein
- the first preceding-stage terminal and a second preceding-stage terminal among the plurality of preceding-stage terminals are connected respectively to different master processing circuits.
A communication system comprising a master unit and a plurality of I/O units connected to the master unit and configured to transmit a signal between the master unit and a device,
- wherein the master unit includes:
- a plurality of master processing circuits configured to perform signal processing;
- and
- a plurality of branch-line terminals connected respectively to the different master processing circuits,
- wherein each of the plurality of I/O units includes:
- a plurality of preceding-stage terminals configured to be connected to the master unit provided in a preceding stage of the I/O unit or to another I/O unit provided in the preceding stage;
- a plurality of subsequent-stage terminals configured to be connected to another I/O unit provided in a subsequent stage of the I/O unit, the subsequent-stage terminals being connected respectively to the different preceding-stage terminals;
- and
- a slave processing circuit connected to the first preceding-stage terminal among the plurality of preceding-stage terminals and to a subsequent-stage terminal among the subsequent-stage terminals that is connected to the first preceding-stage terminal, the slave processing circuit being configured to perform signal processing, and
- wherein
- in each of the plurality of I/O units, the first preceding-stage terminal and the second preceding-stage terminal of the plurality of preceding-stage terminals are connected respectively to different master processing circuits,
- the plurality of I/O units include:
- a plurality of first I/O units the slave processing circuits of which are connected to a first master processing circuit of the master processing circuits;
- and
- a plurality of second I/O units the slave processing circuits of which are connected to a second master processing circuit of the master processing circuits that is different from the first master processing circuit.
Dependencies are inferred from the claim text.