US 12,717,246 B2 · One-dimensional overlay marks

Abstract

Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.

Claims23

Dependent claims

A semiconductor die, comprising:

a plurality of overlay marks, including:
a first overlay mark at a first position on the semiconductor die, wherein the first overlay mark includes a first set of patterns having a first orientation, wherein the first overlay mark does not include patterns having a second orientation substantially orthogonal to the first orientation;
and
a second overlay mark at a second position on the semiconductor die, wherein the second overlay mark includes a second set of patterns having the second orientation, wherein the second overlay mark does not include patterns having the first orientation, and wherein the second position is non-overlapping with the first position.

1 more element

An electronic device, comprising:

processing circuitry, memory circuitry, or communication circuitry on an integrated circuit die, wherein the integrated circuit die comprises:
a plurality of overlay marks, including:
a first overlay mark at a first position on the integrated circuit die, wherein the first overlay mark includes a first set of patterns having a first orientation, wherein the first overlay mark does not include patterns having a second orientation substantially orthogonal to the first orientation;
and
a second overlay mark at a second position on the integrated circuit die, wherein the second overlay mark includes a second set of patterns having the second orientation, wherein the second overlay mark does not include patterns having the first orientation, and wherein the second position is non-overlapping with the first position.

2 more elements

Dependencies are inferred from the claim text.

One-dimensional overlay marks

Life of this patent

One-dimensional overlay marks

Life of this patent

Abstract

Claims23