Semiconductor device

A semiconductor device comprising:

• a first conductive pattern;
• a second conductive pattern;
• a third conductive pattern;
• a fourth conductive pattern;
• a plurality of first semiconductor chips, each first semiconductor chip having
• a front face,
• a back face that is coupled to the first conductive pattern, and
• a switching device formed in said each first semiconductor chip, the switching device having a high-potential electrode at the back face and a low-potential electrode at the front face;
• a plurality of second semiconductor chips, each second semiconductor chip having
• a front face,
• a back face that is coupled to the first conductive pattern, and
• a diode device formed in said each second semiconductor chip, the diode device having a cathode electrode at the back face thereof and an anode electrode at the front face thereof;
• a plurality of first wires, respectively coupling the low-potential electrodes of the plurality of switching devices and the second conductive pattern;
• and
• a plurality of second wires, respectively coupling the anode electrodes of the plurality of diode devices and the second conductive pattern, each of the plurality of second wires having a length substantially equal to a length of each of the plurality of first wires, wherein
• the plurality of first semiconductor chips and the plurality of second semiconductor chips are arranged on the first conductive pattern in two rows that includes a first row and a second row, each row being in a first direction and including at least one of the plurality of first semiconductor chips and at least one of the plurality of second semiconductor chips, the first direction being parallel to a predetermined side of the first conductive pattern,
• the plurality of first wires and the plurality of second wires are each in a second direction orthogonal to the first direction,
• each of the plurality of first semiconductor chips in the first row has a control electrode that is connected, via a third wire, to the third conductive pattern,
• each of the plurality of first semiconductor chips in the second row has a control electrode that is connected, via a fourth wire, to the fourth conductive pattern, and
• in a plan view, the first and second conductive patterns are located between the third conductive pattern and the fourth conductive pattern.