Semiconductor package including surface with reduced visual variation

A semiconductor package comprising:

• a circuit board including a wiring structure;
• first and second semiconductor chips on the circuit board and connected to the wiring structure;
• a dummy chip on the circuit board, positioned between the first and second semiconductor chips, and having a rounded edge between an upper surface and a side surface thereof;
• and
• a molded member on the circuit board and surrounding the first and second semiconductor chips and the dummy chip and covering upper surfaces of the first and second semiconductor chips and the upper surface of the dummy chip,
• wherein the dummy chip is free of through vias extending therethrough,
• wherein a vertical spacing between the upper surface of the dummy chip and an upper surface of the molded member is less than a vertical spacing between the upper surfaces of the first and second semiconductor chips and the upper surface of the molded member,
• wherein the dummy chip is directly bonded to the circuit board by a bonding layer,
• wherein the bonding layer is formed of a non-conductive material, and
• wherein a width of the upper surface of the dummy chip is smaller than a width of a lower surface of the dummy chip.