3D fan-out packaging structure of interconnection system with ultra-high density and method for manufacturing the same

A method for manufacturing a 3D fan-out packaging structure of an interconnection system with ultra-high density, comprising:

• 1) Forming a first insulating layer over a support substrate, and disposing first metal solder pads in the first insulating layer, wherein the first metal solder pads comprise a first type of the first metal solder pads and a second type of the first metal solder pads;
• 2) Forming one or more metal pillars, wherein each of the one or more metal pillars is arranged to align and attach to one of the first type of the first metal solder pads;
• 3) Providing a first chip;
• bonding a second insulating layer to the first insulating layer through non-soldering hybrid bonding;
• forming second metal solder pads in the second insulating layer;
• aligning and connecting each of the second type of the first metal solder pads with one of the second metal solder pads in a one-to-one correspondence through the hybrid bonding;
• and
• attaching a first surface of the first chip to the second insulating layer and the second metal solder pads;
• 4) Disposing a first encapsulating layer on the first chip and the one or more metal pillars, and planarizing the first encapsulating layer to expose a second surface of the first chip and top surfaces of the one or more metal pillars, wherein the first surface and the second surface of the first chip are opposite to each other;
• 5) Forming a first rewiring layer over the first encapsulating layer, wherein the first rewiring layer comprises a first dielectric layer, and a first wiring metal layer disposed in the first dielectric layer and electrically connected to the one or more metal pillars;
• 6) Removing the support substrate to expose the first insulating layer and the first metal solder pads, forming a second rewiring layer on an exposed surface of the first insulating layer, wherein the second rewiring layer comprises a second dielectric layer, and a second metal layer disposed in the second dielectric layer and electrically connected to the one or more metal pillars, and forming solder balls on a surface of the second wiring metal layer;
• and
• 7) Mounting a second chip to the first rewiring layer and forming a second encapsulating layer on a top and side surfaces of the second chip.