Via array in a redistribution layer structure for stress relief

An integrated circuit (IC) structure, comprising:

• a semiconductor substrate;
• an interconnect structure formed over the substrate;
• and
• a redistribution layer (RDL) structure formed over the interconnect structure, wherein the RDL structure includes:
• a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure;
• a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure;
• and
• a RDL top portion over the RDL pad portion and the RDL signal routing portion, the RDL top portion connecting the RDL pad portion and the RDL signal routing portion together,
• wherein the multiple vias of the pad via array includes perimeter vias disposed along edges of the RDL pad portion and a center block via surrounded by the perimeter vias, wherein the center block via has a larger surface area than each of the perimeter vias,
• wherein each of the perimeter vias are spaced closer to another one of the perimeter vias than to the signal routing via.

An integrated circuit (IC) structure, comprising:

• a semiconductor substrate;
• an interconnect structure formed over the substrate;
• and
• a redistribution layer (RDL) structure formed over the interconnect structure, wherein the RDL structure includes:
• a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure, wherein the multiple vias include multiple smaller perimeter vias surrounding a bigger center via;
• a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure;
• and
• a RDL top portion over the RDL pad portion and the RDL signal routing portion, the RDL top portion connecting the RDL pad portion and the RDL signal routing portion together,
• wherein the first top metal line has a first length along a first direction, the second top metal line has a second length along the first direction, and the first length is greater than the second length,
• wherein the first top metal line has a bottom surface free of contact from any metal features, and the second top metal line has a bottom surface in direct contact with a metal via routing to a semiconductor device of the substrate.