US 12,713,924 B2Granted

Device, method, and system to protect through-dielectric vias of a composite chiplet

AssigneeIntel Corporation

InventorsAdel Elsherbini, Mohammad Enamul Kabir, Johanna Swan, Omkar Karhade, Kimin Jun, Feras Eid, Shawna Liff, Xavier Brun, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Haris Khan Niazi

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Abstract

Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

Claims15

Dependent claims

A device comprising:

a first tile which extends vertically through a first level;
a second tile which extends vertically through a second level which is over the first level;
a first layer of a first insulator material which extends vertically between the first level and the second level;
a second layer of a second insulator material which extends vertically through the second level;
a first plurality of conductive vias which each extend through the first layer in a region under the second tile, the first plurality of conductive vias each electrically coupled to respective integrated circuitry of the second tile;
and
a first annular structure which extends through the first layer and which surrounds the first plurality of conductive vias in the first layer;
wherein:
the first tile is electrically coupled to a circuit structure which is disposed in the second layer;
respective first ends of the first plurality of conductive vias are each at a top of the first layer;
respective second ends of the first plurality of conductive vias are each at a bottom of the first layer;
the first annular structure forms a barrier which is contiguous both around the first plurality of conductive vias, and from the top of the first layer to the bottom of the first layer, wherein a first contiguous portion of the first insulator material is separated by the barrier from a second contiguous portion of the first insulator material;
the first contiguous portion extends around and adjoins an exterior sidewall of the first annular structure;
the second contiguous portion adjoins an interior sidewall of the first annular structure, wherein the second contiguous portion further adjoins and extends around each of the first plurality of conductive vias;
and
one of the first contiguous portion or the second contiguous portion further extends around and adjoins the first tile.

13 more elements

A system comprising:

a microprocessor;
and
a memory coupled to the microprocessor, wherein at least one of the memory or the microprocessor comprises:
a first tile which extends vertically through a first level;
a second tile which extends vertically through a second level which is over the first level;
a first layer of a first insulator material which extends vertically between the first level and the second level;
a second layer of a second insulator material which extends vertically through the second level;
a first plurality of conductive vias which each extend through the first layer in a region under the second tile, the first plurality of conductive vias each electrically coupled to respective integrated circuitry of the second tile;
and
a first annular structure which extends through the first layer and which surrounds the first plurality of conductive vias in the first layer;
wherein:
the first tile is electrically coupled to a circuit structure which is disposed in the second layer;
respective first ends of the first plurality of conductive vias are each at a top of the first layer;
respective second ends of the first plurality of conductive vias are each at a bottom of the first layer;
the first annular structure forms a barrier which is contiguous both around the first plurality of conductive vias, and from the top of the first layer to the bottom of the first layer, wherein a first contiguous portion of the first insulator material is separated by the barrier from a second contiguous portion of the first insulator material;
the first contiguous portion extends around and adjoins an exterior sidewall of the first annular structure;
the second contiguous portion adjoins an interior sidewall of the first annular structure, wherein the second contiguous portion further adjoins and extends around each of the first plurality of conductive vias;
and
one of the first contiguous portion or the second contiguous portion further extends around and adjoins the first tile.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/891,704Filed 19 Aug 2022
Published: US 2024/0063147 A122 Feb 2024
Granted: 18 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10W 42/00
Arrangements for protection of devices
H10W 42/273
Characterised by their shapes or dispositions: the arrangements being between laterally adjacent chips, e.g. walls between chips
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 74/01
Encapsulations, e.g. protective coatings: manufacture or treatment