Engineered dielectric profile for high aspect-ratio 3D NAND structures

Abstract

Methods and apparatus of engineered dielectric profile for high aspect-ratio (AR) 3D NAND structures. The 3D NAND structures comprise a semiconductor structure having multiple stacked memory tiers comprising 2D arrays of memory cells that are charged using vertical structures formed in the semiconductor structure. The memory tiers comprise wordline layers interposed between isolation layers. The vertical structures, such as memory holes or trenches, have a dielectric (e.g., a tunnel dielectric) formed along sidewalls of holes or trenches having a cross-section profile where a thickness of the dielectric at a bottom wordline layer is thicker than the dielectric thickness for at least a portion of wordline layers above the bottom wordline layer. In one example, formation of the tunnel dielectric employs a sandwich design of engineered profile method in which a selective deposition of dielectric is deposited at the bottom sections of the vertical structures while the rest of the structure is un-altered.

Dependencies are inferred from the claim text.