Semiconductor package and method for manufacturing the same

A semiconductor package, comprising:

• a first structure including a plurality of first vias, a first insulation layer surrounding side surfaces of the plurality of first vias, a plurality of first connection pads on the plurality of first vias, a first insulation member on the first insulation layer, and a second insulation member on the first insulation layer and surrounding the first insulation layer,
• the first insulation member including a plurality of through openings in which the plurality of first connection pads are disposed, such that each corresponding first connection pad among the plurality of first connection pads is on a corresponding first via among the plurality of first vias and in a corresponding through opening among the plurality of through openings,
• a height of the first insulation member being higher than heights of the plurality of first connection pads,
• a height of the second insulation member being lower than the heights of the plurality of first connection pads, and
• outermost through openings among the plurality of through openings including a first inner side surface defined by a side surface of the first insulation member and a second inner side surface defined by a side surface of the second insulation member;
• a second structure on the first structure,
• the second structure including a plurality of second connection pads, a third insulation member surrounding the plurality of second connection pads, a plurality of second vias on the plurality of second connection pads, and a second insulation layer surrounding the plurality of second vias, wherein
• each corresponding second via among the plurality of second vias is on a corresponding second connection pad among the plurality of second connection pads;
• and
• a plurality of connection members between the first structure and the second structure.

A method for manufacturing a semiconductor structure, the method comprising:

• forming a plurality of connection pads on a substrate base, the substrate base including a plurality of vias and an insulation layer surrounding side surfaces of the plurality of vias;
• applying a first solder resist on the substrate base and the plurality of connection pads;
• forming a plurality of first through openings in the first solder resist such that the plurality of connection pads are exposed;
• applying a second solder resist in the plurality of first through openings and on the first solder resist;
• and
• removing the second solder resist of an edge region of the substrate base, such that the first solder resist of the edge region of the substrate base is exposed, while forming a plurality of second through openings in the second solder resist such that the plurality of connection pads are exposed, wherein
• a height of the first solder resist is lower than a height of the plurality of connection pads, and
• a sum of the height of the first solder resist and a height of the second solder resist is larger than heights of the plurality of connection pads.