Three-dimensional semiconductor memory device and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a first substrate that includes a cell array region and a contact region that extends from the cell array region;
• a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the first substrate;
• a second dielectric layer on the stack structure;
• a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure;
• a selection mold structure on the stack structure and the second dielectric layer;
• a third dielectric layer on the selection mold structure;
• a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug;
• and
• a spacer dielectric layer between the selection mold structure and a sidewall of the capping through contact,
• wherein the selection mold structure includes a selection semiconductor layer.

An electronic system, comprising:

• a first substrate that includes a cell array region and a contact region that extends from the cell array region;
• a three-dimensional semiconductor memory device that includes a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, a dielectric layer on the cell array structure, and an input/output pad on the dielectric layer and connected to the peripheral circuit structure;
• and
• a controller connected to the three-dimensional semiconductor memory device through the input/output pad,
• wherein the cell array structure includes:
• a second substrate on the peripheral circuit structure;
• a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the second substrate;
• a second dielectric layer on the stack structure;
• a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure;
• a selection mold structure on the stack structure and the second dielectric layer;
• a third dielectric layer on the selection mold structure;
• and
• a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug,
• wherein the dummy through contact has a second width in a direction that is parallel to a top surface of the first substrate,
• wherein the capping through contact has a first width in the direction that is parallel to the top surface of the first substrate,
• wherein the second width is greater than the first width, and
• wherein the selection mold structure includes a selection semiconductor layer.