Semiconductor devices and method of manufacturing the same

A method of manufacturing a semiconductor device comprising:

• forming a first conductive pattern on which a first stopper layer is formed and a second conductive pattern on which a second stopper layer is formed on a substrate;
• forming a first interlayer insulating layer on the first conductive pattern and the second conductive pattern;
• exposing at least a portion of the first interlayer insulating layer formed on a first region of the substrate on which the first conductive pattern is present and forming a photoresist pattern on the first interlayer insulating layer formed on a second region of the substrate on which the second conductive pattern is present;
• etching the at least a portion of the first interlayer insulating layer on the first region of the substrate;
• performing first polishing to expose an upper surface of the first stopper layer;
• etching the first stopper layer;
• forming a second interlayer insulating layer on the first conductive pattern and the second conductive pattern;
• and
• performing second polishing to expose an upper surface of the first conductive pattern,
• wherein a first pattern density of the first conductive pattern is greater than a second pattern density of the second conductive pattern.

A method of manufacturing a semiconductor device comprising:

• forming a first conductive pattern on which a first stopper layer is formed and a second conductive pattern on which a second stopper layer is formed on a lower insulating layer;
• forming a first interlayer insulating layer on the first conductive pattern and the second conductive pattern;
• exposing at least a portion of the first interlayer insulating layer on a first region of the lower insulating layer on which the first conductive pattern is present and forming a photoresist pattern on the first interlayer insulating layer on a second region of the lower insulating layer on which the second conductive pattern is present;
• etching the at least a portion of the first interlayer insulating layer on the first region;
• performing first polishing to expose an upper surface of the first stopper layer;
• etching the first stopper layer;
• forming a second interlayer insulating layer on the first conductive pattern and the second conductive pattern;
• and
• performing second polishing to expose an upper surface of the first conductive pattern,
• wherein a first pattern density of the first conductive pattern is greater than a second pattern density of the second conductive pattern.