Semiconductor memory device
AssigneeKioxia Corporation
InventorKenichi Murooka
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.
Claims21
A semiconductor memory device, comprising:
- first wiring extending in a first direction:
- a second wiring being apart from the first wiring in a second direction crossing the first direction, the second wiring extending in the first direction;
- a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing in the first and the second directions;
- a fourth wiring being apart from the third wiring in the second direction, the fourth wiring extending in the third direction:
- a first two-terminal memory element being provided between the first wiring and the third wiring;
- a second two-terminal memory element being provided between the second wiring and the third wiring, and separated from the first two-terminal memory element by the third wiring;
- a third two-terminal memory element being provided between the second wiring and the fourth wiring;
- a fifth wiring being connected to the third wiring and extending in the second direction;
- a sixth wiring being connected to the fourth wiring and extending in the second direction;
- and
- a circuit including a first decoder and a second decoder, the first decoder being connected to the fifth wiring and the sixth wiring, the second decoder being connected to the first wiring, wherein the first decoder applies a first voltage to the fifth wiring and a second voltage to the sixth wiring, and the second decoder applies a third voltage to the first wiring.
A semiconductor memory device, comprising:
- a plurality of column line layers, each column line layer including a plurality of column lines;
- a plurality of rows of row lines interleaved with the column lines of the plurality of column line layers, such that a row of row lines is positioned between each consecutive pair of column lines in each column line layers;
- a plurality of memory cells including two-terminal memory elements,
- wherein a first memory element of a pair of two-terminal memory elements is disposed between a first row line and a first column line, and wherein a second memory element of a pair of two-terminal memory elements is disposed between the first column line and a second row line,
- wherein the first memory element and the second memory element are separated by the first column line and aligned perpendicular to an extending direction of the first column line,
- wherein the first row line is coupled to an upper row line connecting line, and the second row line is coupled to a lower row line connecting line;
- and
- a circuit including a first decoder coupled to the upper row line connecting line and the lower row line connecting line, and a second decoder coupled to the first column line, wherein the first decoder applies a first voltage to the upper row line connecting line and a second voltage to the lower row line connecting line, and the second decoder applies a third voltage to the first column line.
A semiconductor memory device, comprising:
- a memory cell array block including:
- a plurality of horizontal line layers, each horizontal line layer including a plurality of horizontal lines;
- a plurality of vertical lines interleaved with the horizontal lines of the plurality of horizontal line layers such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer;
- a plurality of memory cells including two-terminal memory elements configured integrally between the horizontal lines and each vertical line;
- a first vertical line connecting line layer above the memory cells having a first plurality of vertical line connecting lines;
- and
- a second vertical line connecting line layer below the memory cells having a second plurality of vertical line connecting lines, wherein
- each vertical line is positioned between each consecutive pair of two-terminal memory elements on each horizontal line layer and separates the consecutive pair of two-terminal memory elements, and
- each memory element is disposed between a vertical line and an adjacent horizontal line.
Dependencies are inferred from the claim text.